Huacai Chen b2edcfc814 MIPS: Loongson: Add Loongson-3A R2 basic support ... Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R2 revision of Loongson-3A: - Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache). - I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is 64 bytes. - 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way set-associative). - Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/ Execute-Inhibit. [ralf@linux-mips.org: Resolved merge conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12751/ Patchwork: https://patchwork.linux-mips.org/patch/13136/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2016-05-13 14:02:14 +02:00
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acpi_init.c	MIPS: Loongson-3: Move chipset ACPI code from drivers to arch	2016-05-13 14:02:13 +02:00
cop2-ex.c
hpet.c	MIPS: hpet: Choose a safe value for the ETIME check	2016-01-22 02:00:49 +01:00
irq.c	MIPS: Loongson-3: Adjust irq dispatch to speedup processing	2016-05-13 14:02:14 +02:00
Makefile	MIPS: Loongson-3: Move chipset ACPI code from drivers to arch	2016-05-13 14:02:13 +02:00
numa.c	MIPS: Loongson-3: Reserve 32MB for RS780E integrated GPU	2016-05-09 12:00:03 +02:00
platform.c
smp.c	MIPS: Loongson: Add Loongson-3A R2 basic support	2016-05-13 14:02:14 +02:00
smp.h