d04c56f73c
This implements a lazy strategy for disabling interrupts. This means that local_irq_disable() et al. just clear the 'interrupts are enabled' flag in the paca. If an interrupt comes along, the interrupt entry code notices that interrupts are supposed to be disabled, and clears the EE bit in SRR1, clears the 'interrupts are hard-enabled' flag in the paca, and returns. This means that interrupts only actually get disabled in the processor when an interrupt comes along. When interrupts are enabled by local_irq_enable() et al., the code sets the interrupts-enabled flag in the paca, and then checks whether interrupts got hard-disabled. If so, it also sets the EE bit in the MSR to hard-enable the interrupts. This has the potential to improve performance, and also makes it easier to make a kernel that can boot on iSeries and on other 64-bit machines, since this lazy-disable strategy is very similar to the soft-disable strategy that iSeries already uses. This version renames paca->proc_enabled to paca->soft_enabled, and changes a couple of soft-disables in the kexec code to hard-disables, which should fix the crash that Michael Ellerman saw. This doesn't yet use a reserved CR field for the soft_enabled and hard_enabled flags. This applies on top of Stephen Rothwell's patches to make it possible to build a combined iSeries/other kernel. Signed-off-by: Paul Mackerras <paulus@samba.org>
114 lines
3.5 KiB
C
114 lines
3.5 KiB
C
/*
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* include/asm-powerpc/paca.h
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*
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* This control block defines the PACA which defines the processor
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* specific data for each logical processor on the system.
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* There are some pointers defined that are utilized by PLIC.
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*
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* C 2001 PPC 64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_PACA_H
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#define _ASM_POWERPC_PACA_H
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#ifdef __KERNEL__
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#include <asm/types.h>
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#include <asm/lppaca.h>
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#include <asm/mmu.h>
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register struct paca_struct *local_paca asm("r13");
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#define get_paca() local_paca
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#define get_lppaca() (get_paca()->lppaca_ptr)
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#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
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struct task_struct;
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/*
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* Defines the layout of the paca.
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*
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* This structure is not directly accessed by firmware or the service
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* processor except for the first two pointers that point to the
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* lppaca area and the ItLpRegSave area for this CPU. The lppaca
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* object is currently contained within the PACA but it doesn't need
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* to be.
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*/
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struct paca_struct {
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/*
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* Because hw_cpu_id, unlike other paca fields, is accessed
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* routinely from other CPUs (from the IRQ code), we stick to
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* read-only (after boot) fields in the first cacheline to
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* avoid cacheline bouncing.
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*/
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/*
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* MAGIC: These first two pointers can't be moved - they're
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* accessed by the firmware
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*/
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struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
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#ifdef CONFIG_PPC_ISERIES
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void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
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#endif /* CONFIG_PPC_ISERIES */
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/*
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* MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
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* load lock_token and paca_index with a single lwz
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* instruction. They must travel together and be properly
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* aligned.
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*/
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u16 lock_token; /* Constant 0x8000, used in locks */
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u16 paca_index; /* Logical processor number */
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u64 kernel_toc; /* Kernel TOC address */
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u64 stab_real; /* Absolute address of segment table */
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u64 stab_addr; /* Virtual address of segment table */
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void *emergency_sp; /* pointer to emergency stack */
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u64 data_offset; /* per cpu data offset */
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s16 hw_cpu_id; /* Physical processor number */
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u8 cpu_start; /* At startup, processor spins until */
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/* this becomes non-zero. */
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/*
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* Now, starting in cacheline 2, the exception save areas
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*/
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/* used for most interrupts/exceptions */
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u64 exgen[10] __attribute__((aligned(0x80)));
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u64 exmc[10]; /* used for machine checks */
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u64 exslb[10]; /* used for SLB/segment table misses
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* on the linear mapping */
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mm_context_t context;
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u16 vmalloc_sllp;
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u16 slb_cache[SLB_CACHE_ENTRIES];
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u16 slb_cache_ptr;
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/*
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* then miscellaneous read-write fields
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*/
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struct task_struct *__current; /* Pointer to current */
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u64 kstack; /* Saved Kernel stack addr */
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u64 stab_rr; /* stab/slb round-robin counter */
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u64 saved_r1; /* r1 save for RTAS calls */
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u64 saved_msr; /* MSR saved here by enter_rtas */
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u8 soft_enabled; /* irq soft-enable flag */
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u8 hard_enabled; /* set if irqs are enabled in MSR */
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u8 io_sync; /* writel() needs spin_unlock sync */
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/* Stuff for accurate time accounting */
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u64 user_time; /* accumulated usermode TB ticks */
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u64 system_time; /* accumulated system TB ticks */
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u64 startpurr; /* PURR/TB value snapshot */
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struct slb_shadow *slb_shadow_ptr;
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};
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extern struct paca_struct paca[];
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void setup_boot_paca(void);
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PACA_H */
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