Siddha, Suresh B 2b0918758d [PATCH] x86_64: x86_64/i386 fix Intel cache detection code assumption about threads sharing ... Fix the Intel cache detection code assumption that number of threads sharing the cache will either be equal to number of HT or core siblings. This also cleans up the code in general a bit. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>		2005-11-14 19:55:16 -08:00
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alpha
arm	[PATCH] ARM: Reverted 2918/1: [update] Base port of Comdial MP1000 platfrom	2005-11-04 17:28:34 +00:00
arm26
cris
frv
h8300
i386	[PATCH] x86_64: x86_64/i386 fix Intel cache detection code assumption about threads sharing	2005-11-14 19:55:16 -08:00
ia64	[PATCH] x86_64: Set compatibility flag for 4GB zone on IA64	2005-11-14 19:55:13 -08:00
m32r
m68k
m68knommu
mips
parisc
powerpc	Merge master.kernel.org:/pub/scm/linux/kernel/git/paulus/powerpc-merge	2005-11-04 16:27:50 -08:00
ppc	powerpc: Merge smp.c and smp.h	2005-11-05 10:33:55 +11:00
ppc64	powerpc: Merge smp.c and smp.h	2005-11-05 10:33:55 +11:00
s390
sh
sh64
sparc
sparc64
um
v850
x86_64	[PATCH] x86-64/i386: Intel HT, Multi core detection fixes	2005-11-14 19:55:16 -08:00
xtensa