Kever Yang 29e9446851 clk: rockchip: fix clock select order for rk3288 usbphy480m_src ... According to rk3288 trm, the mux selector locate at bit[12:11] of CRU_CLKSEL13_CON shows: 2'b00: select HOST0 USB pll clock (clk_otgphy1) 2'b01: select HOST1 USB pll clock (clk_otgphy2) 2'b10: select OTG USB pll clock (clk_otgphy0) The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3 - clk_otgphy0 -> USB PHY OTG - clk_otgphy1 -> USB PHY host0 - clk_otgphy2 -> USB PHY host1 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2014-11-16 00:40:19 +01:00
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clk-cpu.c	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
clk-pll.c	clk: rockchip: change pll rate without a clk-notifier	2014-09-27 17:57:04 +02:00
clk-rk3188.c	clk: rockchip: fix rk3188 hsadc_frac definition	2014-11-07 23:41:14 +01:00
clk-rk3288.c	clk: rockchip: fix clock select order for rk3288 usbphy480m_src	2014-11-16 00:40:19 +01:00
clk-rockchip.c
clk.c	clk: rockchip: disable unused clocks	2014-11-04 22:52:51 +01:00
clk.h	clk: rockchip: change PLL setting for better clock jitter	2014-10-29 20:27:20 +01:00
Makefile	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00