192 lines
4.9 KiB
C
192 lines
4.9 KiB
C
#ifndef __ASM_SH_DMA_MAPPING_H
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#define __ASM_SH_DMA_MAPPING_H
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#include <linux/mm.h>
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#include <asm/scatterlist.h>
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#include <asm/cacheflush.h>
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#include <asm/io.h>
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extern struct bus_type pci_bus_type;
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/* arch/sh/mm/consistent.c */
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extern void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *handle);
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extern void consistent_free(void *vaddr, size_t size);
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extern void consistent_sync(void *vaddr, size_t size, int direction);
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#define dma_supported(dev, mask) (1)
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static inline int dma_set_mask(struct device *dev, u64 mask)
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{
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if (!dev->dma_mask || !dma_supported(dev, mask))
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return -EIO;
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*dev->dma_mask = mask;
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return 0;
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}
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static inline void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag)
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{
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if (sh_mv.mv_consistent_alloc) {
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void *ret;
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ret = sh_mv.mv_consistent_alloc(dev, size, dma_handle, flag);
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if (ret != NULL)
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return ret;
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}
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return consistent_alloc(flag, size, dma_handle);
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}
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static inline void dma_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle)
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{
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if (sh_mv.mv_consistent_free) {
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int ret;
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ret = sh_mv.mv_consistent_free(dev, size, vaddr, dma_handle);
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if (ret == 0)
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return;
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}
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consistent_free(vaddr, size);
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#define dma_is_consistent(d, h) (1)
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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consistent_sync(vaddr, size, (int)dir);
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}
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static inline dma_addr_t dma_map_single(struct device *dev,
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void *ptr, size_t size,
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enum dma_data_direction dir)
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{
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#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
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if (dev->bus == &pci_bus_type)
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return virt_to_bus(ptr);
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#endif
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dma_cache_sync(dev, ptr, size, dir);
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return virt_to_bus(ptr);
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}
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#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
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static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction dir)
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{
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int i;
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for (i = 0; i < nents; i++) {
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#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
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dma_cache_sync(dev, page_address(sg[i].page) + sg[i].offset,
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sg[i].length, dir);
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#endif
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sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset;
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}
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return nents;
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}
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#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
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static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir)
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{
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return dma_map_single(dev, page_address(page) + offset, size, dir);
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}
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static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
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size_t size, enum dma_data_direction dir)
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{
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dma_unmap_single(dev, dma_address, size, dir);
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}
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static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir)
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{
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#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
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if (dev->bus == &pci_bus_type)
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return;
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#endif
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dma_cache_sync(dev, bus_to_virt(dma_handle), size, dir);
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}
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static inline void dma_sync_single_range(struct device *dev,
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dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction dir)
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{
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#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
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if (dev->bus == &pci_bus_type)
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return;
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#endif
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dma_cache_sync(dev, bus_to_virt(dma_handle) + offset, size, dir);
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}
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static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
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int nelems, enum dma_data_direction dir)
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{
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int i;
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for (i = 0; i < nelems; i++) {
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#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
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dma_cache_sync(dev, page_address(sg[i].page) + sg[i].offset,
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sg[i].length, dir);
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#endif
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sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset;
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}
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}
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static inline void dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir)
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{
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dma_sync_single(dev, dma_handle, size, dir);
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}
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static inline void dma_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle,
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size_t size,
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enum dma_data_direction dir)
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{
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dma_sync_single(dev, dma_handle, size, dir);
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}
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static inline void dma_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sg, int nelems,
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enum dma_data_direction dir)
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{
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dma_sync_sg(dev, sg, nelems, dir);
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}
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static inline void dma_sync_sg_for_device(struct device *dev,
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struct scatterlist *sg, int nelems,
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enum dma_data_direction dir)
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{
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dma_sync_sg(dev, sg, nelems, dir);
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}
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static inline int dma_get_cache_alignment(void)
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{
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/*
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* Each processor family will define its own L1_CACHE_SHIFT,
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* L1_CACHE_BYTES wraps to this, so this is always safe.
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*/
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return L1_CACHE_BYTES;
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}
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static inline int dma_mapping_error(dma_addr_t dma_addr)
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{
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return dma_addr == 0;
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}
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#endif /* __ASM_SH_DMA_MAPPING_H */
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