b13159afb4
Consolidate all of the copies of MAX_MODULE_HARDRESET_WAIT and MAX_MODULE_SOFTRESET_WAIT into one place, arch/arm/mach-omap2/prm.h. Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
134 lines
3.6 KiB
C
134 lines
3.6 KiB
C
/*
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* OMAP2+ MPU WD_TIMER-specific code
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/platform_data/omap-wd-timer.h>
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#include "omap_hwmod.h"
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#include "omap_device.h"
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#include "wd_timer.h"
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#include "common.h"
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#include "prm.h"
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#include "soc.h"
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/*
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* In order to avoid any assumptions from bootloader regarding WDT
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* settings, WDT module is reset during init. This enables the watchdog
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* timer. Hence it is required to disable the watchdog after the WDT reset
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* during init. Otherwise the system would reboot as per the default
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* watchdog timer registers settings.
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*/
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#define OMAP_WDT_WPS 0x34
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#define OMAP_WDT_SPR 0x48
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int omap2_wd_timer_disable(struct omap_hwmod *oh)
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{
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void __iomem *base;
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if (!oh) {
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pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
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return -EINVAL;
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}
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base = omap_hwmod_get_mpu_rt_va(oh);
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if (!base) {
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pr_err("%s: Could not get the base address for %s\n",
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oh->name, __func__);
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return -EINVAL;
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}
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/* sequence required to disable watchdog */
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__raw_writel(0xAAAA, base + OMAP_WDT_SPR);
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while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
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cpu_relax();
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__raw_writel(0x5555, base + OMAP_WDT_SPR);
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while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
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cpu_relax();
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return 0;
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}
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/**
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* omap2_wdtimer_reset - reset and disable the WDTIMER IP block
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* @oh: struct omap_hwmod *
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*
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* After the WDTIMER IP blocks are reset on OMAP2/3, we must also take
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* care to execute the special watchdog disable sequence. This is
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* because the watchdog is re-armed upon OCP softreset. (On OMAP4,
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* this behavior was apparently changed and the watchdog is no longer
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* re-armed after an OCP soft-reset.) Returns -ETIMEDOUT if the reset
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* did not complete, or 0 upon success.
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*
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* XXX Most of this code should be moved to the omap_hwmod.c layer
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* during a normal merge window. omap_hwmod_softreset() should be
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* renamed to omap_hwmod_set_ocp_softreset(), and omap_hwmod_softreset()
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* should call the hwmod _ocp_softreset() code.
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*/
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int omap2_wd_timer_reset(struct omap_hwmod *oh)
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{
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int c = 0;
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/* Write to the SOFTRESET bit */
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omap_hwmod_softreset(oh);
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/* Poll on RESETDONE bit */
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omap_test_timeout((omap_hwmod_read(oh,
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oh->class->sysc->syss_offs)
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& SYSS_RESETDONE_MASK),
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MAX_MODULE_SOFTRESET_WAIT, c);
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if (oh->class->sysc->srst_udelay)
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udelay(oh->class->sysc->srst_udelay);
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if (c == MAX_MODULE_SOFTRESET_WAIT)
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pr_warning("%s: %s: softreset failed (waited %d usec)\n",
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__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
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else
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pr_debug("%s: %s: softreset in %d usec\n", __func__,
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oh->name, c);
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return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT :
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omap2_wd_timer_disable(oh);
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}
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static int __init omap_init_wdt(void)
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{
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int id = -1;
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struct platform_device *pdev;
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struct omap_hwmod *oh;
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char *oh_name = "wd_timer2";
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char *dev_name = "omap_wdt";
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struct omap_wd_timer_platform_data pdata;
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if (!cpu_class_is_omap2() || of_have_populated_dt())
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return 0;
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oh = omap_hwmod_lookup(oh_name);
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if (!oh) {
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pr_err("Could not look up wd_timer%d hwmod\n", id);
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return -EINVAL;
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}
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pdata.read_reset_sources = prm_read_reset_sources;
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pdev = omap_device_build(dev_name, id, oh, &pdata,
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sizeof(struct omap_wd_timer_platform_data),
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NULL, 0, 0);
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WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
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dev_name, oh->name);
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return 0;
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}
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subsys_initcall(omap_init_wdt);
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