2856f5e31c
atomic_add_unless as inline. Remove system.h atomic.h circular dependency. I agree (with Andi Kleen) this typeof is not needed and more error prone. All the original atomic.h code that uses cmpxchg (which includes the atomic_add_unless) uses defines instead of inline functions, probably to circumvent a circular dependency between system.h and atomic.h on powerpc (which my patch addresses). Therefore, it makes sense to use inline functions that will provide type checking. atomic_add_unless as inline. Remove system.h atomic.h circular dependency. Digging into the FRV architecture shows me that it is also affected by such a circular dependency. Here is the diff applying this against the rest of my atomic.h patches. It applies over the atomic.h standardization patches. Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
269 lines
6.9 KiB
C
269 lines
6.9 KiB
C
/* system.h: FR-V CPU control definitions
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*
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* Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_SYSTEM_H
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#define _ASM_SYSTEM_H
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#include <linux/linkage.h>
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struct thread_struct;
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/*
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* switch_to(prev, next) should switch from task `prev' to `next'
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* `prev' will never be the same as `next'.
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* The `mb' is to tell GCC not to cache `current' across this call.
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*/
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extern asmlinkage
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struct task_struct *__switch_to(struct thread_struct *prev_thread,
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struct thread_struct *next_thread,
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struct task_struct *prev);
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#define switch_to(prev, next, last) \
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do { \
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(prev)->thread.sched_lr = \
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(unsigned long) __builtin_return_address(0); \
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(last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
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mb(); \
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} while(0)
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/*
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* interrupt flag manipulation
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* - use virtual interrupt management since touching the PSR is slow
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* - ICC2.Z: T if interrupts virtually disabled
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* - ICC2.C: F if interrupts really disabled
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* - if Z==1 upon interrupt:
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* - C is set to 0
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* - interrupts are really disabled
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* - entry.S returns immediately
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* - uses TIHI (TRAP if Z==0 && C==0) #2 to really reenable interrupts
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* - if taken, the trap:
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* - sets ICC2.C
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* - enables interrupts
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*/
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#define local_irq_disable() \
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do { \
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/* set Z flag, but don't change the C flag */ \
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asm volatile(" andcc gr0,gr0,gr0,icc2 \n" \
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: \
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: \
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: "memory", "icc2" \
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); \
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} while(0)
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#define local_irq_enable() \
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do { \
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/* clear Z flag and then test the C flag */ \
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asm volatile(" oricc gr0,#1,gr0,icc2 \n" \
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" tihi icc2,gr0,#2 \n" \
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: \
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: \
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: "memory", "icc2" \
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); \
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} while(0)
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#define local_save_flags(flags) \
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do { \
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typecheck(unsigned long, flags); \
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asm volatile("movsg ccr,%0" \
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: "=r"(flags) \
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: \
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: "memory"); \
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\
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/* shift ICC2.Z to bit 0 */ \
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flags >>= 26; \
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\
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/* make flags 1 if interrupts disabled, 0 otherwise */ \
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flags &= 1UL; \
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} while(0)
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#define irqs_disabled() \
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({unsigned long flags; local_save_flags(flags); flags; })
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#define local_irq_save(flags) \
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do { \
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typecheck(unsigned long, flags); \
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local_save_flags(flags); \
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local_irq_disable(); \
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} while(0)
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#define local_irq_restore(flags) \
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do { \
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typecheck(unsigned long, flags); \
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\
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/* load the Z flag by turning 1 if disabled into 0 if disabled \
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* and thus setting the Z flag but not the C flag */ \
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asm volatile(" xoricc %0,#1,gr0,icc2 \n" \
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/* then test Z=0 and C=0 */ \
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" tihi icc2,gr0,#2 \n" \
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: \
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: "r"(flags) \
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: "memory", "icc2" \
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); \
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\
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} while(0)
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/*
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* real interrupt flag manipulation
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*/
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#define __local_irq_disable() \
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do { \
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unsigned long psr; \
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asm volatile(" movsg psr,%0 \n" \
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" andi %0,%2,%0 \n" \
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" ori %0,%1,%0 \n" \
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" movgs %0,psr \n" \
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: "=r"(psr) \
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: "i" (PSR_PIL_14), "i" (~PSR_PIL) \
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: "memory"); \
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} while(0)
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#define __local_irq_enable() \
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do { \
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unsigned long psr; \
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asm volatile(" movsg psr,%0 \n" \
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" andi %0,%1,%0 \n" \
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" movgs %0,psr \n" \
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: "=r"(psr) \
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: "i" (~PSR_PIL) \
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: "memory"); \
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} while(0)
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#define __local_save_flags(flags) \
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do { \
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typecheck(unsigned long, flags); \
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asm("movsg psr,%0" \
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: "=r"(flags) \
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: \
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: "memory"); \
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} while(0)
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#define __local_irq_save(flags) \
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do { \
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unsigned long npsr; \
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typecheck(unsigned long, flags); \
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asm volatile(" movsg psr,%0 \n" \
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" andi %0,%3,%1 \n" \
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" ori %1,%2,%1 \n" \
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" movgs %1,psr \n" \
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: "=r"(flags), "=r"(npsr) \
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: "i" (PSR_PIL_14), "i" (~PSR_PIL) \
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: "memory"); \
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} while(0)
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#define __local_irq_restore(flags) \
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do { \
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typecheck(unsigned long, flags); \
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asm volatile(" movgs %0,psr \n" \
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: \
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: "r" (flags) \
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: "memory"); \
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} while(0)
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#define __irqs_disabled() \
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((__get_PSR() & PSR_PIL) >= PSR_PIL_14)
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/*
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* Force strict CPU ordering.
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*/
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#define nop() asm volatile ("nop"::)
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#define mb() asm volatile ("membar" : : :"memory")
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#define rmb() asm volatile ("membar" : : :"memory")
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#define wmb() asm volatile ("membar" : : :"memory")
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define read_barrier_depends() do {} while(0)
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#define smp_read_barrier_depends() read_barrier_depends()
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#define HARD_RESET_NOW() \
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do { \
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cli(); \
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} while(1)
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extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2)));
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extern void free_initmem(void);
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#define arch_align_stack(x) (x)
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/*****************************************************************************/
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/*
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* compare and conditionally exchange value with memory
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* - if (*ptr == test) then orig = *ptr; *ptr = test;
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* - if (*ptr != test) then orig = *ptr;
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*/
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#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
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#define cmpxchg(ptr, test, new) \
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({ \
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__typeof__(ptr) __xg_ptr = (ptr); \
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__typeof__(*(ptr)) __xg_orig, __xg_tmp; \
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__typeof__(*(ptr)) __xg_test = (test); \
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__typeof__(*(ptr)) __xg_new = (new); \
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\
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switch (sizeof(__xg_orig)) { \
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case 4: \
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asm volatile( \
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"0: \n" \
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" orcc gr0,gr0,gr0,icc3 \n" \
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" ckeq icc3,cc7 \n" \
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" ld.p %M0,%1 \n" \
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" orcr cc7,cc7,cc3 \n" \
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" sub%I4cc %1,%4,%2,icc0 \n" \
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" bne icc0,#0,1f \n" \
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" cst.p %3,%M0 ,cc3,#1 \n" \
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" \
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" beq icc3,#0,0b \n" \
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"1: \n" \
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: "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp) \
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: "r"(__xg_new), "NPr"(__xg_test) \
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: "memory", "cc7", "cc3", "icc3", "icc0" \
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); \
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break; \
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\
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default: \
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__xg_orig = 0; \
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asm volatile("break"); \
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break; \
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} \
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\
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__xg_orig; \
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})
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#else
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extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
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#define cmpxchg(ptr, test, new) \
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({ \
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__typeof__(ptr) __xg_ptr = (ptr); \
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__typeof__(*(ptr)) __xg_orig; \
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__typeof__(*(ptr)) __xg_test = (test); \
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__typeof__(*(ptr)) __xg_new = (new); \
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\
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switch (sizeof(__xg_orig)) { \
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case 4: __xg_orig = __cmpxchg_32(__xg_ptr, __xg_test, __xg_new); break; \
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default: \
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__xg_orig = 0; \
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asm volatile("break"); \
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break; \
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} \
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\
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__xg_orig; \
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})
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#endif
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#endif /* _ASM_SYSTEM_H */
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