24dc5f33ea
Update libata LLDs to use devres. Core layer is already converted to
support managed LLDs. This patch simplifies initialization and fixes
many resource related bugs in init failure and detach path. For
example, all converted drivers now handle ata_device_add() failure
gracefully without excessive resource rollback code.
As most resources are released automatically on driver detach, many
drivers don't need or can do with much simpler ->{port|host}_stop().
In general, stop callbacks are need iff port or host needs to be given
commands to shut it down. Note that freezing is enough in many cases
and ports are automatically frozen before being detached.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
353 lines
9.2 KiB
C
353 lines
9.2 KiB
C
/*
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* pata_it8213.c - iTE Tech. Inc. IT8213 PATA driver
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*
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* The IT8213 is a very Intel ICH like device for timing purposes, having
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* a similar register layout and the same split clock arrangement. Cable
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* detection is different, and it does not have slave channels or all the
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* clutter of later ICH/SATA setups.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/ata.h>
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#define DRV_NAME "pata_it8213"
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#define DRV_VERSION "0.0.2"
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/**
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* it8213_pre_reset - check for 40/80 pin
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* @ap: Port
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*
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* Perform cable detection for the 8213 ATA interface. This is
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* different to the PIIX arrangement
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*/
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static int it8213_pre_reset(struct ata_port *ap)
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{
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static const struct pci_bits it8213_enable_bits[] = {
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{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
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};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 tmp;
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if (!pci_test_config_bits(pdev, &it8213_enable_bits[ap->port_no]))
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return -ENOENT;
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pci_read_config_byte(pdev, 0x42, &tmp);
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if (tmp & 2) /* The initial docs are incorrect */
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ap->cbl = ATA_CBL_PATA40;
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else
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ap->cbl = ATA_CBL_PATA80;
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return ata_std_prereset(ap);
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}
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/**
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* it8213_probe_reset - Probe specified port on PATA host controller
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* @ap: Port to probe
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void it8213_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, it8213_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
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}
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/**
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* it8213_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: um
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*
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* Set PIO mode for device, in host controller PCI config space.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void it8213_set_piomode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int pio = adev->pio_mode - XFER_PIO_0;
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struct pci_dev *dev = to_pci_dev(ap->host->dev);
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unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
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u16 idetm_data;
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int control = 0;
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/*
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* See Intel Document 298600-004 for the timing programing rules
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* for PIIX/ICH. The 8213 is a clone so very similar
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*/
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static const /* ISP RTC */
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u8 timings[][2] = { { 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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if (pio > 2)
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control |= 1; /* TIME1 enable */
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if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
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control |= 2; /* IORDY enable */
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/* Bit 2 is set for ATAPI on the IT8213 - reverse of ICH/PIIX */
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if (adev->class != ATA_DEV_ATA)
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control |= 4;
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pci_read_config_word(dev, idetm_port, &idetm_data);
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/* Enable PPE, IE and TIME as appropriate */
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if (adev->devno == 0) {
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idetm_data &= 0xCCF0;
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idetm_data |= control;
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idetm_data |= (timings[pio][0] << 12) |
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(timings[pio][1] << 8);
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} else {
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u8 slave_data;
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idetm_data &= 0xCC0F;
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idetm_data |= (control << 4);
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/* Slave timing in seperate register */
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pci_read_config_byte(dev, 0x44, &slave_data);
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slave_data &= 0xF0;
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << 4;
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pci_write_config_byte(dev, 0x44, slave_data);
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}
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idetm_data |= 0x4000; /* Ensure SITRE is enabled */
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pci_write_config_word(dev, idetm_port, idetm_data);
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}
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/**
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* it8213_set_dmamode - Initialize host controller PATA DMA timings
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* @ap: Port whose timings we are configuring
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* @adev: Device to program
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*
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* Set UDMA/MWDMA mode for device, in host controller PCI config space.
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* This device is basically an ICH alike.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void it8213_set_dmamode (struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *dev = to_pci_dev(ap->host->dev);
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u16 master_data;
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u8 speed = adev->dma_mode;
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int devid = adev->devno;
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u8 udma_enable;
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static const /* ISP RTC */
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u8 timings[][2] = { { 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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pci_read_config_word(dev, 0x40, &master_data);
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pci_read_config_byte(dev, 0x48, &udma_enable);
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if (speed >= XFER_UDMA_0) {
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unsigned int udma = adev->dma_mode - XFER_UDMA_0;
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u16 udma_timing;
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u16 ideconf;
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int u_clock, u_speed;
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/* Clocks follow the PIIX style */
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u_speed = min(2 - (udma & 1), udma);
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if (udma == 5)
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u_clock = 0x1000; /* 100Mhz */
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else if (udma > 2)
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u_clock = 1; /* 66Mhz */
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else
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u_clock = 0; /* 33Mhz */
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udma_enable |= (1 << devid);
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/* Load the UDMA mode number */
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pci_read_config_word(dev, 0x4A, &udma_timing);
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udma_timing &= ~(3 << (4 * devid));
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udma_timing |= (udma & 3) << (4 * devid);
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pci_write_config_word(dev, 0x4A, udma_timing);
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/* Load the clock selection */
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pci_read_config_word(dev, 0x54, &ideconf);
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ideconf &= ~(0x1001 << devid);
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ideconf |= u_clock << devid;
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pci_write_config_word(dev, 0x54, ideconf);
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} else {
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/*
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* MWDMA is driven by the PIO timings. We must also enable
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* IORDY unconditionally along with TIME1. PPE has already
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* been set when the PIO timing was set.
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*/
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unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
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unsigned int control;
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u8 slave_data;
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static const unsigned int needed_pio[3] = {
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XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
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};
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int pio = needed_pio[mwdma] - XFER_PIO_0;
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control = 3; /* IORDY|TIME1 */
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/* If the drive MWDMA is faster than it can do PIO then
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we must force PIO into PIO0 */
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if (adev->pio_mode < needed_pio[mwdma])
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/* Enable DMA timing only */
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control |= 8; /* PIO cycles in PIO0 */
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if (devid) { /* Slave */
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master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
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master_data |= control << 4;
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pci_read_config_byte(dev, 0x44, &slave_data);
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slave_data &= (0x0F + 0xE1 * ap->port_no);
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/* Load the matching timing */
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
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pci_write_config_byte(dev, 0x44, slave_data);
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} else { /* Master */
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master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
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and master timing bits */
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master_data |= control;
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master_data |=
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(timings[pio][0] << 12) |
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(timings[pio][1] << 8);
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}
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udma_enable &= ~(1 << devid);
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pci_write_config_word(dev, 0x40, master_data);
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}
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pci_write_config_byte(dev, 0x48, udma_enable);
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}
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static struct scsi_host_template it8213_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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.resume = ata_scsi_device_resume,
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.suspend = ata_scsi_device_suspend,
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};
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static const struct ata_port_operations it8213_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = it8213_set_piomode,
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.set_dmamode = it8213_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = it8213_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_pio_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.port_start = ata_port_start,
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};
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/**
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* it8213_init_one - Register 8213 ATA PCI device with kernel services
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* @pdev: PCI device to register
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* @ent: Entry in it8213_pci_tbl matching with @pdev
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*
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* Called from kernel PCI layer.
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*
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* LOCKING:
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* Inherited from PCI layer (may sleep).
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*
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* RETURNS:
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* Zero on success, or -ERRNO value.
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*/
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static int it8213_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version;
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static struct ata_port_info info = {
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.sht = &it8213_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x1f, /* UDMA 100 */
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.port_ops = &it8213_ops,
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};
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static struct ata_port_info *port_info[2] = { &info, &info };
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev,
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"version " DRV_VERSION "\n");
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/* Current IT8213 stuff is single port */
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return ata_pci_init_one(pdev, port_info, 1);
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}
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static const struct pci_device_id it8213_pci_tbl[] = {
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{ PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8213), },
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{ } /* terminate list */
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};
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static struct pci_driver it8213_pci_driver = {
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.name = DRV_NAME,
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.id_table = it8213_pci_tbl,
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.probe = it8213_init_one,
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.remove = ata_pci_remove_one,
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.suspend = ata_pci_device_suspend,
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.resume = ata_pci_device_resume,
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};
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static int __init it8213_init(void)
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{
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return pci_register_driver(&it8213_pci_driver);
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}
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static void __exit it8213_exit(void)
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{
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pci_unregister_driver(&it8213_pci_driver);
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}
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module_init(it8213_init);
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module_exit(it8213_exit);
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("SCSI low-level driver for the ITE 8213");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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