2239aff6ab
The implementation for memory copy functions on ARM had a (disabled) provision for aligning the source pointer before loading registers with data. Turns out that aligning the _destination_ pointer is much more useful, as the read side is already sufficiently helped with the use of preload. So this changes the definition of the CALGN() macro to target the destination pointer instead, and turns it on for Feroceon processors where the gain is very noticeable. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> |
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| .. | ||
| ashldi3.S | ||
| ashrdi3.S | ||
| backtrace.S | ||
| bitops.h | ||
| changebit.S | ||
| clear_user.S | ||
| clearbit.S | ||
| copy_from_user.S | ||
| copy_page.S | ||
| copy_template.S | ||
| copy_to_user.S | ||
| csumipv6.S | ||
| csumpartial.S | ||
| csumpartialcopy.S | ||
| csumpartialcopygeneric.S | ||
| csumpartialcopyuser.S | ||
| delay.S | ||
| div64.S | ||
| ecard.S | ||
| findbit.S | ||
| floppydma.S | ||
| getuser.S | ||
| io-acorn.S | ||
| io-readsb.S | ||
| io-readsl.S | ||
| io-readsw-armv3.S | ||
| io-readsw-armv4.S | ||
| io-shark.c | ||
| io-writesb.S | ||
| io-writesl.S | ||
| io-writesw-armv3.S | ||
| io-writesw-armv4.S | ||
| lib1funcs.S | ||
| lshrdi3.S | ||
| Makefile | ||
| memchr.S | ||
| memcpy.S | ||
| memmove.S | ||
| memset.S | ||
| memzero.S | ||
| muldi3.S | ||
| putuser.S | ||
| setbit.S | ||
| sha1.S | ||
| strchr.S | ||
| strncpy_from_user.S | ||
| strnlen_user.S | ||
| strrchr.S | ||
| testchangebit.S | ||
| testclearbit.S | ||
| testsetbit.S | ||
| uaccess.S | ||
| ucmpdi2.S | ||