87e29cacb7
Previously this was using a hardcoded 32, use L1_CACHE_BYTES for cacheline alignment instead. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
/* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $
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*
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* include/asm-sh/cache.h
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*
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* Copyright 1999 (C) Niibe Yutaka
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* Copyright 2002, 2003 (C) Paul Mundt
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*/
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#ifndef __ASM_SH_CACHE_H
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#define __ASM_SH_CACHE_H
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#ifdef __KERNEL__
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#include <asm/cpu/cache.h>
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#define SH_CACHE_VALID 1
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#define SH_CACHE_UPDATED 2
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#define SH_CACHE_COMBINED 4
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#define SH_CACHE_ASSOC 8
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
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#ifndef __ASSEMBLY__
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struct cache_info {
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unsigned int ways; /* Number of cache ways */
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unsigned int sets; /* Number of cache sets */
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unsigned int linesz; /* Cache line size (bytes) */
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unsigned int way_size; /* sets * line size */
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/*
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* way_incr is the address offset for accessing the next way
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* in memory mapped cache array ops.
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*/
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unsigned int way_incr;
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unsigned int entry_shift;
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unsigned int entry_mask;
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/*
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* Compute a mask which selects the address bits which overlap between
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* 1. those used to select the cache set during indexing
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* 2. those in the physical page number.
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*/
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unsigned int alias_mask;
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unsigned int n_aliases; /* Number of aliases */
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unsigned long flags;
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_CACHE_H */
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