0259d9eb30
The UART1 is on the fast AHB bridge, not on the slow bus. Cc: stable@vger.kernel.org Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
166 lines
4.1 KiB
C
166 lines
4.1 KiB
C
/*
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*
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* arch/arm/mach-u300/include/mach/u300-regs.h
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*
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*
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* Copyright (C) 2006-2009 ST-Ericsson AB
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* License terms: GNU General Public License (GPL) version 2
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* Basic register address definitions in physical memory and
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* some block definitions for core devices like the timer.
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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*/
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#ifndef __MACH_U300_REGS_H
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#define __MACH_U300_REGS_H
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/*
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* These are the large blocks of memory allocated for I/O.
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* the defines are used for setting up the I/O memory mapping.
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*/
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/* NAND Flash CS0 */
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#define U300_NAND_CS0_PHYS_BASE 0x80000000
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/* NFIF */
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#define U300_NAND_IF_PHYS_BASE 0x9f800000
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/* ALE, CLE offset for FSMC NAND */
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#define PLAT_NAND_CLE (1 << 16)
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#define PLAT_NAND_ALE (1 << 17)
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/* AHB Peripherals */
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#define U300_AHB_PER_PHYS_BASE 0xa0000000
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#define U300_AHB_PER_VIRT_BASE 0xff010000
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/* FAST Peripherals */
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#define U300_FAST_PER_PHYS_BASE 0xc0000000
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#define U300_FAST_PER_VIRT_BASE 0xff020000
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/* SLOW Peripherals */
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#define U300_SLOW_PER_PHYS_BASE 0xc0010000
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#define U300_SLOW_PER_VIRT_BASE 0xff000000
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/* Boot ROM */
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#define U300_BOOTROM_PHYS_BASE 0xffff0000
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#define U300_BOOTROM_VIRT_BASE 0xffff0000
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/* SEMI config base */
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#define U300_SEMI_CONFIG_BASE 0x2FFE0000
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/*
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* AHB peripherals
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*/
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/* AHB Peripherals Bridge Controller */
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#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
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/* Vectored Interrupt Controller 0, servicing 32 interrupts */
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#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
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#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
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/* Vectored Interrupt Controller 1, servicing 32 interrupts */
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#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
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#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
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/* Memory Stick Pro (MSPRO) controller */
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#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
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/* EMIF Configuration Area */
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#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
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/*
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* FAST peripherals
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*/
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/* FAST bridge control */
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#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
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/* MMC/SD controller */
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#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
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/* PCM I2S0 controller */
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#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
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/* PCM I2S1 controller */
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#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
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/* I2C0 controller */
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#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
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/* I2C1 controller */
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#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
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/* SPI controller */
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#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
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/* Fast UART1 on U335 only */
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#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
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/*
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* SLOW peripherals
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*/
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/* SLOW bridge control */
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#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
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/* SYSCON */
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#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
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#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
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/* Watchdog */
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#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
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/* UART0 */
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#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
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/* APP side special timer */
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#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
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#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
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/* Keypad */
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#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
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/* GPIO */
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#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
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/* RTC */
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#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
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/* Bus tracer */
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#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
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/* Event handler (hardware queue) */
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#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
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/* Genric Timer */
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#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
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/* PPM */
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#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
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/*
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* REST peripherals
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*/
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/* ISP (image signal processor) */
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#define U300_ISP_BASE (0xA0008000)
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/* DMA Controller base */
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#define U300_DMAC_BASE (0xC0020000)
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/* MSL Base */
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#define U300_MSL_BASE (0xc0022000)
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/* APEX Base */
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#define U300_APEX_BASE (0xc0030000)
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/* Video Encoder Base */
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#define U300_VIDEOENC_BASE (0xc0080000)
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/* XGAM Base */
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#define U300_XGAM_BASE (0xd0000000)
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#endif
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