f8fffa4583
quad core 8 socket system will have apic id lifting.the apic id range could be [4, 0x23]. and apic_is_clustered_box will think that need to three clusters and that is larger than 2. So it is treated as a clustered_box. and will get: Marking TSC unstable due to TSCs unsynchronized even if the CPUs have X86_FEATURE_CONSTANT_TSC set. this quick fix will check if the cpu is from AMD. but vsmp still needs that checking... this patch is fix to make sure that vsmp not to be passed. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
146 lines
3.5 KiB
C
146 lines
3.5 KiB
C
#ifndef _ASM_X86_APIC_H
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#define _ASM_X86_APIC_H
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#include <linux/pm.h>
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#include <linux/delay.h>
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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#define Dprintk(x...)
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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extern void generic_apic_probe(void);
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#ifdef CONFIG_X86_LOCAL_APIC
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extern int apic_verbosity;
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extern int timer_over_8254;
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extern int local_apic_timer_c2_ok;
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extern int local_apic_timer_disabled;
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extern int apic_runs_main_timer;
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extern int ioapic_force;
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extern int disable_apic;
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extern int disable_apic_timer;
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extern unsigned boot_cpu_id;
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/*
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* Basic functions accessing APICs.
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*/
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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extern int is_vsmp_box(void);
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#else
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#define apic_write native_apic_write
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#define apic_write_atomic native_apic_write_atomic
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#define apic_read native_apic_read
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#define setup_boot_clock setup_boot_APIC_clock
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#define setup_secondary_clock setup_secondary_APIC_clock
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static int inline is_vsmp_box(void)
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{
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return 0;
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}
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#endif
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static inline void native_apic_write(unsigned long reg, u32 v)
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{
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*((volatile u32 *)(APIC_BASE + reg)) = v;
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}
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static inline void native_apic_write_atomic(unsigned long reg, u32 v)
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{
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(void) xchg((u32*)(APIC_BASE + reg), v);
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}
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static inline u32 native_apic_read(unsigned long reg)
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{
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return *((volatile u32 *)(APIC_BASE + reg));
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}
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extern void apic_wait_icr_idle(void);
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extern u32 safe_apic_wait_icr_idle(void);
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extern int get_physical_broadcast(void);
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#ifdef CONFIG_X86_GOOD_APIC
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# define FORCE_READ_AROUND_WRITE 0
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# define apic_read_around(x)
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# define apic_write_around(x, y) apic_write((x), (y))
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#else
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# define FORCE_READ_AROUND_WRITE 1
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# define apic_read_around(x) apic_read(x)
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# define apic_write_around(x, y) apic_write_atomic((x), (y))
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#endif
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static inline void ack_APIC_irq(void)
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{
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction:
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* - a single rmw on Pentium/82489DX
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* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write_around(APIC_EOI, 0);
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}
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extern int lapic_get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void connect_bsp_APIC(void);
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extern void disconnect_bsp_APIC(int virt_wire_setup);
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extern void disable_local_APIC(void);
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extern void lapic_shutdown(void);
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extern int verify_local_APIC(void);
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extern void cache_APIC_registers(void);
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extern void sync_Arb_IDs(void);
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extern void init_bsp_APIC(void);
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extern void setup_local_APIC(void);
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extern void end_local_APIC_setup(void);
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extern void init_apic_mappings(void);
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extern void setup_boot_APIC_clock(void);
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extern void setup_secondary_APIC_clock(void);
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extern int APIC_init_uniprocessor(void);
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extern void enable_NMI_through_LVT0(void);
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/*
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* On 32bit this is mach-xxx local
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*/
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#ifdef CONFIG_X86_64
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extern void setup_apic_routing(void);
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#endif
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extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
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extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
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extern int apic_is_clustered_box(void);
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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#define local_apic_timer_c2_ok 1
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#endif /* __ASM_APIC_H */
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