a9311cfed2
The Discovery Duo (MV78xx0) has two x4 PCIe ports which can either be used in x4 mode or in quad x1 mode. This patch adds an accessor function to the generic plat-orion PCIe handling code to detect in which of the two modes we're running (which is determined by strap pins and/or configured by the bootloader). Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
33 lines
1.2 KiB
C
33 lines
1.2 KiB
C
/*
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* include/asm-arm/plat-orion/pcie.h
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*
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* Marvell Orion SoC PCIe handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_PLAT_ORION_PCIE_H
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#define __ASM_PLAT_ORION_PCIE_H
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u32 orion_pcie_dev_id(void __iomem *base);
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u32 orion_pcie_rev(void __iomem *base);
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int orion_pcie_link_up(void __iomem *base);
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int orion_pcie_x4_mode(void __iomem *base);
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int orion_pcie_get_local_bus_nr(void __iomem *base);
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void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
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void orion_pcie_setup(void __iomem *base,
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struct mbus_dram_target_info *dram);
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int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val);
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int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val);
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int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val);
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int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 val);
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#endif
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