f4db56ffd4
Some SoCs need a different chip_delay value. Signed-off-by: Saeed Bishara <saeed@marvell.com> Acked-by: Jörn Engel <joern@logfs.org> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
26 lines
588 B
C
26 lines
588 B
C
/*
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* include/asm-arm/plat-orion/orion_nand.h
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_PLAT_ORION_ORION_NAND_H
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#define __ASM_PLAT_ORION_ORION_NAND_H
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/*
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* Device bus NAND private data
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*/
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struct orion_nand_data {
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struct mtd_partition *parts;
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u32 nr_parts;
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u8 ale; /* address line number connected to ALE */
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u8 cle; /* address line number connected to CLE */
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u8 width; /* buswidth */
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u8 chip_delay;
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};
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#endif
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