1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
80 lines
2.2 KiB
ArmAsm
80 lines
2.2 KiB
ArmAsm
/*
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* linux/arch/arm/lib/copypage.S
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*
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* Copyright (C) 1995-1999 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* ASM optimised string functions
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/constants.h>
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.text
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.align 5
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/*
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* ARMv4 optimised copy_user_page
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*
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* We flush the destination cache lines just before we write the data into the
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* corresponding address. Since the Dcache is read-allocate, this removes the
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* Dcache aliasing issue. The writes will be forwarded to the write buffer,
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* and merged as appropriate.
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*
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* Note: We rely on all ARMv4 processors implementing the "invalidate D line"
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* instruction. If your processor does not supply this, you have to write your
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* own copy_user_page that does the right thing.
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*/
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ENTRY(v4wb_copy_user_page)
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stmfd sp!, {r4, lr} @ 2
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mov r2, #PAGE_SZ/64 @ 1
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ldmia r1!, {r3, r4, ip, lr} @ 4
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1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
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stmia r0!, {r3, r4, ip, lr} @ 4
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ldmia r1!, {r3, r4, ip, lr} @ 4+1
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stmia r0!, {r3, r4, ip, lr} @ 4
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ldmia r1!, {r3, r4, ip, lr} @ 4
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mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
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stmia r0!, {r3, r4, ip, lr} @ 4
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ldmia r1!, {r3, r4, ip, lr} @ 4
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subs r2, r2, #1 @ 1
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stmia r0!, {r3, r4, ip, lr} @ 4
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ldmneia r1!, {r3, r4, ip, lr} @ 4
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bne 1b @ 1
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mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB
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ldmfd sp!, {r4, pc} @ 3
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.align 5
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/*
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* ARMv4 optimised clear_user_page
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*
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* Same story as above.
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*/
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ENTRY(v4wb_clear_user_page)
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str lr, [sp, #-4]!
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mov r1, #PAGE_SZ/64 @ 1
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mov r2, #0 @ 1
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mov r3, #0 @ 1
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mov ip, #0 @ 1
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mov lr, #0 @ 1
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1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
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stmia r0!, {r2, r3, ip, lr} @ 4
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stmia r0!, {r2, r3, ip, lr} @ 4
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mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
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stmia r0!, {r2, r3, ip, lr} @ 4
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stmia r0!, {r2, r3, ip, lr} @ 4
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subs r1, r1, #1 @ 1
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bne 1b @ 1
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mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB
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ldr pc, [sp], #4
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__INITDATA
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.type v4wb_user_fns, #object
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ENTRY(v4wb_user_fns)
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.long v4wb_clear_user_page
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.long v4wb_copy_user_page
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.size v4wb_user_fns, . - v4wb_user_fns
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