02ab3f7079
This is the second version of the shared interrupt controller patch for the sh architecture, fixing up handling of intc_reg_fns[]. The three main advantages with this controller over the existing ones are: - Both priority (ipr) and bitmap (intc2) registers are supported - External pin sense configuration is supported, ie edge vs level triggered - CPU/Board specific code maps 1:1 with datasheet for easy verification This controller can easily coexist with the current IPR and INTC2 controllers, but the idea is that CPUs/Boards should be moved over to this controller over time so we have a single code base to maintain. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
11 lines
296 B
Makefile
11 lines
296 B
Makefile
#
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# Makefile for the Linux/SuperH CPU-specifc IRQ handlers.
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#
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obj-y += imask.o
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obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
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obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o
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obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o
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obj-$(CONFIG_CPU_HAS_INTC_IRQ) += intc.o
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obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o
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