e7841be50f
Loongson-3B is a 8-cores processor. In general it looks like there are two Loongson-3A integrated in one chip: 8 cores are separated into two groups (two NUMA node), each node has its own local memory. Of course there are some differences between one Loongson-3B and two Loongson-3A. E.g., the base addresses of IPI registers of each node are not the same; Loongson-3A use ChipConfig register to enable/disable clock, but Loongson-3B use FreqControl register instead. There are two revision of Loongson-3B, the first revision is called as Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the second revision is called as Loongson-3B1500, whose frequency is 1.5GHz and has a PRid 0x6307. Both revisions has a bug that clock cannot be disabled at runtime, but this will be fixed in future. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7188/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
31 lines
747 B
C
31 lines
747 B
C
#ifndef __LOONGSON_SMP_H_
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#define __LOONGSON_SMP_H_
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/* for Loongson-3 smp support */
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extern unsigned long long smp_group[4];
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/* 4 groups(nodes) in maximum in numa case */
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#define SMP_CORE_GROUP0_BASE (smp_group[0])
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#define SMP_CORE_GROUP1_BASE (smp_group[1])
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#define SMP_CORE_GROUP2_BASE (smp_group[2])
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#define SMP_CORE_GROUP3_BASE (smp_group[3])
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/* 4 cores in each group(node) */
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#define SMP_CORE0_OFFSET 0x000
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#define SMP_CORE1_OFFSET 0x100
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#define SMP_CORE2_OFFSET 0x200
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#define SMP_CORE3_OFFSET 0x300
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/* ipi registers offsets */
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#define STATUS0 0x00
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#define EN0 0x04
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#define SET0 0x08
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#define CLEAR0 0x0c
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#define STATUS1 0x10
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#define MASK1 0x14
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#define SET1 0x18
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#define CLEAR1 0x1c
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#define BUF 0x20
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#endif
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