The intention of using port_mask in SFF init helpers was to eventually support exoctic configurations such as combination of legacy and native port on the same controller. This never became actually necessary and the related code always has been subtly broken one way or the other. Now that new init model is in place, there is no reason to make common helpers capable of handling all corner cases. Exotic cases can simply dealt within LLDs as necessary. This patch removes port_mask handling in SFF init helpers. SFF init helpers don't take n_ports argument and interpret it into port_mask anymore. All information is carried via port_info. n_ports argument is dropped and always two ports are allocated. LLD can tell SFF to skip certain port by marking it dummy. Note that SFF code has been treating unuvailable ports this way for a long time until recent breakage fix from Linus and is consistent with how other drivers handle with unavailable ports. This fixes 1-port legacy host handling still broken after the recent native mode fix and simplifies SFF init logic. The following changes are made... * ata_pci_init_native_host() and ata_init_legacy_host() both now try to initialized whatever they can and mark failed ports dummy. They return 0 if any port is successfully initialized. * ata_pci_prepare_native_host() and ata_pci_init_one() now doesn't take n_ports argument. All info should be specified via port_info array. Always two ports are allocated. * ata_pci_init_bmdma() exported to be used by LLDs in exotic cases. * port_info handling in all LLDs are standardized - all port_info arrays are const stack variable named ppi. Unless the second port is different from the first, its port_info is specified as NULL (tells libata that it's identical to the last non-NULL port_info). * pata_hpt37x/hpt3x2n: don't modify static variable directly. Make an on-stack copy instead as ata_piix does. * pata_uli: It has 4 ports instead of 2. Don't use ata_pci_prepare_native_host(). Allocate the host explicitly and use init helpers. It's simple enough. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
526 lines
14 KiB
C
526 lines
14 KiB
C
/*
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* pata_artop.c - ARTOP ATA controller driver
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*
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* (C) 2006 Red Hat <alan@redhat.com>
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*
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* Based in part on drivers/ide/pci/aec62xx.c
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* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
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* 865/865R fixes for Macintosh card version from a patch to the old
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* driver by Thibaut VARENE <varenet@parisc-linux.org>
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* When setting the PCI latency we must set 0x80 or higher for burst
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* performance Alessandro Zummo <alessandro.zummo@towertech.it>
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*
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* TODO
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* 850 serialization once the core supports it
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* Investigate no_dsc on 850R
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* Clock detect
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/ata.h>
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#define DRV_NAME "pata_artop"
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#define DRV_VERSION "0.4.2"
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/*
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* The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
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* get PCI bus speed functionality we leave this as 0. Its a variable
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* for when we get the functionality and also for folks wanting to
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* test stuff.
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*/
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static int clock = 0;
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static int artop6210_pre_reset(struct ata_port *ap, unsigned long deadline)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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const struct pci_bits artop_enable_bits[] = {
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{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
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{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
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};
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if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
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return -ENOENT;
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return ata_std_prereset(ap, deadline);
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}
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/**
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* artop6210_error_handler - Probe specified port on PATA host controller
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* @ap: Port to probe
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6210_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, artop6210_pre_reset,
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ata_std_softreset, NULL,
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ata_std_postreset);
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}
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/**
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* artop6260_pre_reset - check for 40/80 pin
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* @ap: Port
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* @deadline: deadline jiffies for the operation
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*
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* The ARTOP hardware reports the cable detect bits in register 0x49.
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* Nothing complicated needed here.
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*/
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static int artop6260_pre_reset(struct ata_port *ap, unsigned long deadline)
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{
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static const struct pci_bits artop_enable_bits[] = {
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{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
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{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
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};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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/* Odd numbered device ids are the units with enable bits (the -R cards) */
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if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
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return -ENOENT;
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return ata_std_prereset(ap, deadline);
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}
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/**
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* artop6260_cable_detect - identify cable type
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* @ap: Port
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*
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* Identify the cable type for the ARTOp interface in question
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*/
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static int artop6260_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 tmp;
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pci_read_config_byte(pdev, 0x49, &tmp);
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if (tmp & (1 << ap->port_no))
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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}
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/**
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* artop6260_error_handler - Probe specified port on PATA host controller
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* @ap: Port to probe
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6260_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, artop6260_pre_reset,
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ata_std_softreset, NULL,
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ata_std_postreset);
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}
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/**
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* artop6210_load_piomode - Load a set of PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device
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* @pio: PIO mode
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*
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* Set PIO mode for device, in host controller PCI config space. This
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* is used both to set PIO timings in PIO mode and also to set the
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* matching PIO clocking for UDMA, as well as the MWDMA timings.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int dn = adev->devno + 2 * ap->port_no;
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const u16 timing[2][5] = {
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{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
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{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
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};
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/* Load the PIO timing active/recovery bits */
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pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
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}
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/**
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* artop6210_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device we are configuring
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*
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* Set PIO mode for device, in host controller PCI config space. For
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* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
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* the event UDMA is used the later call to set_dmamode will set the
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* bits as required.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int dn = adev->devno + 2 * ap->port_no;
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u8 ultra;
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artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
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/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
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pci_read_config_byte(pdev, 0x54, &ultra);
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ultra &= ~(3 << (2 * dn));
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pci_write_config_byte(pdev, 0x54, ultra);
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}
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/**
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* artop6260_load_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device we are configuring
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* @pio: PIO mode
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*
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* Set PIO mode for device, in host controller PCI config space. The
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* ARTOP6260 and relatives store the timing data differently.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int dn = adev->devno + 2 * ap->port_no;
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const u8 timing[2][5] = {
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{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
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{ 0x70, 0x7A, 0x78, 0x43, 0x41 }
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};
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/* Load the PIO timing active/recovery bits */
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pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
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}
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/**
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* artop6260_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device we are configuring
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*
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* Set PIO mode for device, in host controller PCI config space. For
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* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
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* the event UDMA is used the later call to set_dmamode will set the
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* bits as required.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 ultra;
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artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
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/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
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pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
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ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
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pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
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}
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/**
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* artop6210_set_dmamode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device whose timings we are configuring
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*
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* Set DMA mode for device, in host controller PCI config space.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int pio;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int dn = adev->devno + 2 * ap->port_no;
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u8 ultra;
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if (adev->dma_mode == XFER_MW_DMA_0)
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pio = 1;
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else
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pio = 4;
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/* Load the PIO timing active/recovery bits */
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artop6210_load_piomode(ap, adev, pio);
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pci_read_config_byte(pdev, 0x54, &ultra);
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ultra &= ~(3 << (2 * dn));
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/* Add ultra DMA bits if in UDMA mode */
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if (adev->dma_mode >= XFER_UDMA_0) {
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u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
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if (mode == 0)
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mode = 1;
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ultra |= (mode << (2 * dn));
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}
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pci_write_config_byte(pdev, 0x54, ultra);
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}
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/**
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* artop6260_set_dmamode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device we are configuring
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*
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* Set DMA mode for device, in host controller PCI config space. The
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* ARTOP6260 and relatives store the timing data differently.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int pio = adev->pio_mode - XFER_PIO_0;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 ultra;
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if (adev->dma_mode == XFER_MW_DMA_0)
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pio = 1;
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else
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pio = 4;
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/* Load the PIO timing active/recovery bits */
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artop6260_load_piomode(ap, adev, pio);
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/* Add ultra DMA bits if in UDMA mode */
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pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
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ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
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if (adev->dma_mode >= XFER_UDMA_0) {
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u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
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if (mode == 0)
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mode = 1;
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ultra |= (mode << (4 * adev->devno));
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}
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pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
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}
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static struct scsi_host_template artop_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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static const struct ata_port_operations artop6210_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = artop6210_set_piomode,
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.set_dmamode = artop6210_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = artop6210_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = ata_cable_40wire,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_port_start,
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};
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static const struct ata_port_operations artop6260_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = artop6260_set_piomode,
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.set_dmamode = artop6260_set_dmamode,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = artop6260_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = artop6260_cable_detect,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_port_start,
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};
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/**
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* artop_init_one - Register ARTOP ATA PCI device with kernel services
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* @pdev: PCI device to register
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* @ent: Entry in artop_pci_tbl matching with @pdev
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*
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* Called from kernel PCI layer.
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*
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* LOCKING:
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* Inherited from PCI layer (may sleep).
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*
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* RETURNS:
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* Zero on success, or -ERRNO value.
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*/
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static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
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{
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static int printed_version;
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static const struct ata_port_info info_6210 = {
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.sht = &artop_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = ATA_UDMA2,
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.port_ops = &artop6210_ops,
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};
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static const struct ata_port_info info_626x = {
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.sht = &artop_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = ATA_UDMA4,
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.port_ops = &artop6260_ops,
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};
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static const struct ata_port_info info_626x_fast = {
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.sht = &artop_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
|
.udma_mask = ATA_UDMA5,
|
|
.port_ops = &artop6260_ops,
|
|
};
|
|
const struct ata_port_info *ppi[] = { NULL, NULL };
|
|
|
|
if (!printed_version++)
|
|
dev_printk(KERN_DEBUG, &pdev->dev,
|
|
"version " DRV_VERSION "\n");
|
|
|
|
if (id->driver_data == 0) { /* 6210 variant */
|
|
ppi[0] = &info_6210;
|
|
ppi[1] = &ata_dummy_port_info;
|
|
/* BIOS may have left us in UDMA, clear it before libata probe */
|
|
pci_write_config_byte(pdev, 0x54, 0);
|
|
/* For the moment (also lacks dsc) */
|
|
printk(KERN_WARNING "ARTOP 6210 requires serialize functionality not yet supported by libata.\n");
|
|
printk(KERN_WARNING "Secondary ATA ports will not be activated.\n");
|
|
}
|
|
else if (id->driver_data == 1) /* 6260 */
|
|
ppi[0] = &info_626x;
|
|
else if (id->driver_data == 2) { /* 6260 or 6260 + fast */
|
|
unsigned long io = pci_resource_start(pdev, 4);
|
|
u8 reg;
|
|
|
|
ppi[0] = &info_626x;
|
|
if (inb(io) & 0x10)
|
|
ppi[0] = &info_626x_fast;
|
|
/* Mac systems come up with some registers not set as we
|
|
will need them */
|
|
|
|
/* Clear reset & test bits */
|
|
pci_read_config_byte(pdev, 0x49, ®);
|
|
pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);
|
|
|
|
/* PCI latency must be > 0x80 for burst mode, tweak it
|
|
* if required.
|
|
*/
|
|
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, ®);
|
|
if (reg <= 0x80)
|
|
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
|
|
|
|
/* Enable IRQ output and burst mode */
|
|
pci_read_config_byte(pdev, 0x4a, ®);
|
|
pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
|
|
|
|
}
|
|
|
|
BUG_ON(ppi[0] == NULL);
|
|
|
|
return ata_pci_init_one(pdev, ppi);
|
|
}
|
|
|
|
static const struct pci_device_id artop_pci_tbl[] = {
|
|
{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
|
|
{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
|
|
{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
|
|
{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
|
|
{ PCI_VDEVICE(ARTOP, 0x0009), 2 },
|
|
|
|
{ } /* terminate list */
|
|
};
|
|
|
|
static struct pci_driver artop_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = artop_pci_tbl,
|
|
.probe = artop_init_one,
|
|
.remove = ata_pci_remove_one,
|
|
};
|
|
|
|
static int __init artop_init(void)
|
|
{
|
|
return pci_register_driver(&artop_pci_driver);
|
|
}
|
|
|
|
static void __exit artop_exit(void)
|
|
{
|
|
pci_unregister_driver(&artop_pci_driver);
|
|
}
|
|
|
|
module_init(artop_init);
|
|
module_exit(artop_exit);
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|