885014bcf2
Only one MIPS development board actually supports enabling/disabling DMA coherency at runtime, so it's not a good idea to push the overhead of checking that configuration setting onto every other supported target as well. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5912/
25 lines
546 B
C
25 lines
546 B
C
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
|
|
*
|
|
*/
|
|
#ifndef __ASM_DMA_COHERENCE_H
|
|
#define __ASM_DMA_COHERENCE_H
|
|
|
|
#ifdef CONFIG_DMA_MAYBE_COHERENT
|
|
extern int coherentio;
|
|
extern int hw_coherentio;
|
|
#else
|
|
#ifdef CONFIG_DMA_COHERENT
|
|
#define coherentio 1
|
|
#else
|
|
#define coherentio 0
|
|
#endif
|
|
#define hw_coherentio 0
|
|
#endif /* CONFIG_DMA_MAYBE_COHERENT */
|
|
|
|
#endif
|