Julien CHAUVEAU 12c0a0e81e clk: rockchip: fix rk3188 USB HSIC PHY clock divider ... The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11). Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2014-11-23 01:55:14 +01:00
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clk-cpu.c	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
clk-pll.c	clk: rockchip: change pll rate without a clk-notifier	2014-09-27 17:57:04 +02:00
clk-rk3188.c	clk: rockchip: fix rk3188 USB HSIC PHY clock divider	2014-11-23 01:55:14 +01:00
clk-rk3288.c	clk: rockchip: fix clock select order for rk3288 usbphy480m_src	2014-11-16 00:40:19 +01:00
clk-rockchip.c
clk.c	clk: rockchip: disable unused clocks	2014-11-04 22:52:51 +01:00
clk.h	clk: rockchip: change PLL setting for better clock jitter	2014-10-29 20:27:20 +01:00
Makefile	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00