b8b52471e8
Certain bridge chips use a GPIO to indicate the cable status instead of the I_DP_HPD pin. This adds an optional device-tree property, "samsung,hpd-gpio", to the exynos-dp controller which indicates that the specified GPIO should be used for hotplug detection. The GPIO is then set up as an edge-triggered interrupt where the rising edge indicates hotplug-in and the falling edge indicates hotplug-out. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
109 lines
3.0 KiB
Plaintext
109 lines
3.0 KiB
Plaintext
The Exynos display port interface should be configured based on
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the type of panel connected to it.
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We use two nodes:
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-dp-controller node
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-dptx-phy node(defined inside dp-controller node)
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For the DP-PHY initialization, we use the dptx-phy node.
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Required properties for dptx-phy: deprecated, use phys and phy-names
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-reg: deprecated
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Base address of DP PHY register.
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-samsung,enable-mask: deprecated
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The bit-mask used to enable/disable DP PHY.
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For the Panel initialization, we read data from dp-controller node.
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Required properties for dp-controller:
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-compatible:
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should be "samsung,exynos5-dp".
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-reg:
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physical base address of the controller and length
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of memory mapped region.
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-interrupts:
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interrupt combiner values.
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-clocks:
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from common clock binding: handle to dp clock.
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-clock-names:
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from common clock binding: Shall be "dp".
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-interrupt-parent:
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phandle to Interrupt combiner node.
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-phys:
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from general PHY binding: the phandle for the PHY device.
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-phy-names:
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from general PHY binding: Should be "dp".
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-samsung,color-space:
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input video data format.
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COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
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-samsung,dynamic-range:
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dynamic range for input video data.
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VESA = 0, CEA = 1
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-samsung,ycbcr-coeff:
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YCbCr co-efficients for input video.
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COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
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-samsung,color-depth:
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number of bits per colour component.
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COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
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-samsung,link-rate:
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link rate supported by the panel.
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LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
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-samsung,lane-count:
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number of lanes supported by the panel.
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LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
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- display-timings: timings for the connected panel as described by
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Documentation/devicetree/bindings/video/display-timing.txt
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Optional properties for dp-controller:
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-interlaced:
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interlace scan mode.
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Progressive if defined, Interlaced if not defined
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-vsync-active-high:
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VSYNC polarity configuration.
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High if defined, Low if not defined
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-hsync-active-high:
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HSYNC polarity configuration.
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High if defined, Low if not defined
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-samsung,hpd-gpio:
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Hotplug detect GPIO.
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Indicates which GPIO should be used for hotplug
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detection
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Example:
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SOC specific portion:
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dp-controller {
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compatible = "samsung,exynos5-dp";
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reg = <0x145b0000 0x10000>;
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interrupts = <10 3>;
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interrupt-parent = <&combiner>;
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clocks = <&clock 342>;
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clock-names = "dp";
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phys = <&dp_phy>;
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phy-names = "dp";
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};
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Board Specific portion:
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dp-controller {
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samsung,color-space = <0>;
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samsung,dynamic-range = <0>;
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samsung,ycbcr-coeff = <0>;
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samsung,color-depth = <1>;
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samsung,link-rate = <0x0a>;
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samsung,lane-count = <4>;
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display-timings {
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native-mode = <&lcd_timing>;
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lcd_timing: 1366x768 {
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clock-frequency = <70589280>;
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hactive = <1366>;
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vactive = <768>;
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hfront-porch = <40>;
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hback-porch = <40>;
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hsync-len = <32>;
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vback-porch = <10>;
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vfront-porch = <12>;
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vsync-len = <6>;
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};
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};
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};
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