aab42ed51b
Taishan (440GX) has the first PHY (EMAC2) mapped at PHY address 1 and the 2nd PHY (EMAC3) at PHY address 3. Use "phy-address" to correctly describe this instead of "phy-map". Signed-off-by: Stefan Roese <sr@denx.de> Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
428 lines
11 KiB
Plaintext
428 lines
11 KiB
Plaintext
/*
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* Device Tree Source for IBM/AMCC Taishan
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*
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* Copyright 2007 IBM Corp.
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* Hugh Blemings <hugh@au.ibm.com> based off code by
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* Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <1>;
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model = "amcc,taishan";
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compatible = "amcc,taishan";
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dcr-parent = <&{/cpus/cpu@0}>;
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aliases {
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ethernet0 = &EMAC2;
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ethernet1 = &EMAC3;
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serial0 = &UART0;
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serial1 = &UART1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,440GX";
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reg = <0x00000000>;
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clock-frequency = <800000000>; // 800MHz
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timebase-frequency = <0>; // Filled in by zImage
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i-cache-line-size = <50>;
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d-cache-line-size = <50>;
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i-cache-size = <32768>; /* 32 kB */
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d-cache-size = <32768>; /* 32 kB */
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dcr-controller;
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dcr-access-method = "native";
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
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};
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UICB0: interrupt-controller-base {
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compatible = "ibm,uic-440gx", "ibm,uic";
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interrupt-controller;
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cell-index = <3>;
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dcr-reg = <0x200 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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UIC0: interrupt-controller0 {
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compatible = "ibm,uic-440gx", "ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0x0c0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */
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interrupt-parent = <&UICB0>;
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};
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UIC1: interrupt-controller1 {
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compatible = "ibm,uic-440gx", "ibm,uic";
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interrupt-controller;
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cell-index = <1>;
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dcr-reg = <0x0d0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x3 0x4 0x2 0x4>; /* cascade */
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interrupt-parent = <&UICB0>;
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};
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UIC2: interrupt-controller2 {
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compatible = "ibm,uic-440gx", "ibm,uic";
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interrupt-controller;
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cell-index = <2>; /* was 1 */
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dcr-reg = <0x210 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x5 0x4 0x4 0x4>; /* cascade */
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interrupt-parent = <&UICB0>;
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};
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CPC0: cpc {
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compatible = "ibm,cpc-440gp";
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dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
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// FIXME: anything else?
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};
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L2C0: l2c {
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compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
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dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
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0x030 0x008>; /* L2 cache DCR's */
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cache-line-size = <32>; /* 32 bytes */
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cache-size = <262144>; /* L2, 256K */
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interrupt-parent = <&UIC2>;
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interrupts = <0x17 0x1>;
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};
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plb {
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compatible = "ibm,plb-440gx", "ibm,plb4";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <160000000>; // 160MHz
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SDRAM0: memory-controller {
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compatible = "ibm,sdram-440gp";
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dcr-reg = <0x010 0x002>;
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// FIXME: anything else?
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};
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SRAM0: sram {
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compatible = "ibm,sram-440gp";
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dcr-reg = <0x020 0x008 0x00a 0x001>;
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};
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DMA0: dma {
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// FIXME: ???
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compatible = "ibm,dma-440gp";
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dcr-reg = <0x100 0x027>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-440gx", "ibm,mcmal2";
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dcr-reg = <0x180 0x062>;
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num-tx-chans = <4>;
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num-rx-chans = <4>;
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interrupt-parent = <&MAL0>;
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interrupts = <0x0 0x1 0x2 0x3 0x4>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
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/*RXEOB*/ 0x1 &UIC0 0xb 0x4
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/*SERR*/ 0x2 &UIC1 0x0 0x4
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/*TXDE*/ 0x3 &UIC1 0x1 0x4
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/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
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interrupt-map-mask = <0xffffffff>;
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};
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POB0: opb {
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compatible = "ibm,opb-440gx", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Wish there was a nicer way of specifying a full 32-bit
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range */
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ranges = <0x00000000 0x00000001 0x00000000 0x80000000
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0x80000000 0x00000001 0x80000000 0x80000000>;
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dcr-reg = <0x090 0x00b>;
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interrupt-parent = <&UIC1>;
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interrupts = <0x7 0x4>;
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clock-frequency = <80000000>; // 80MHz
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EBC0: ebc {
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compatible = "ibm,ebc-440gx", "ibm,ebc";
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dcr-reg = <0x012 0x002>;
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#address-cells = <2>;
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#size-cells = <1>;
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clock-frequency = <80000000>; // 80MHz
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/* ranges property is supplied by zImage
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* based on firmware's configuration of the
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* EBC bridge */
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interrupts = <0x5 0x4>;
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interrupt-parent = <&UIC1>;
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nor_flash@0,0 {
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compatible = "cfi-flash";
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bank-width = <4>;
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device-width = <2>;
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reg = <0x0 0x0 0x4000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x0 0x180000>;
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};
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partition@180000 {
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label = "root";
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reg = <0x180000 0x200000>;
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};
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partition@380000 {
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label = "user";
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reg = <0x380000 0x3bc0000>;
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};
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partition@3f40000 {
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label = "env";
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reg = <0x3f40000 0x80000>;
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};
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partition@3fc0000 {
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label = "u-boot";
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reg = <0x3fc0000 0x40000>;
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};
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};
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};
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UART0: serial@40000200 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x40000200 0x00000008>;
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virtual-reg = <0xe0000200>;
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clock-frequency = <11059200>;
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current-speed = <115200>; /* 115200 */
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interrupt-parent = <&UIC0>;
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interrupts = <0x0 0x4>;
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};
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UART1: serial@40000300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x40000300 0x00000008>;
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virtual-reg = <0xe0000300>;
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clock-frequency = <11059200>;
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current-speed = <115200>; /* 115200 */
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interrupt-parent = <&UIC0>;
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interrupts = <0x1 0x4>;
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};
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IIC0: i2c@40000400 {
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/* FIXME */
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compatible = "ibm,iic-440gp", "ibm,iic";
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reg = <0x40000400 0x00000014>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x2 0x4>;
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};
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IIC1: i2c@40000500 {
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/* FIXME */
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compatible = "ibm,iic-440gp", "ibm,iic";
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reg = <0x40000500 0x00000014>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x3 0x4>;
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};
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GPIO0: gpio@40000700 {
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/* FIXME */
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compatible = "ibm,gpio-440gp";
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reg = <0x40000700 0x00000020>;
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};
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ZMII0: emac-zmii@40000780 {
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compatible = "ibm,zmii-440gx", "ibm,zmii";
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reg = <0x40000780 0x0000000c>;
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};
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RGMII0: emac-rgmii@40000790 {
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compatible = "ibm,rgmii";
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reg = <0x40000790 0x00000008>;
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};
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TAH0: emac-tah@40000b50 {
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compatible = "ibm,tah-440gx", "ibm,tah";
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reg = <0x40000b50 0x00000030>;
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};
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TAH1: emac-tah@40000d50 {
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compatible = "ibm,tah-440gx", "ibm,tah";
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reg = <0x40000d50 0x00000030>;
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};
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EMAC0: ethernet@40000800 {
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unused = <0x1>;
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device_type = "network";
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compatible = "ibm,emac-440gx", "ibm,emac4";
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interrupt-parent = <&UIC1>;
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interrupts = <0x1c 0x4 0x1d 0x4>;
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reg = <0x40000800 0x00000074>;
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local-mac-address = [000000000000]; // Filled in by zImage
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mal-device = <&MAL0>;
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mal-tx-channel = <0>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <1500>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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phy-mode = "rmii";
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phy-map = <0x00000001>;
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zmii-device = <&ZMII0>;
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zmii-channel = <0>;
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};
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EMAC1: ethernet@40000900 {
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unused = <0x1>;
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device_type = "network";
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compatible = "ibm,emac-440gx", "ibm,emac4";
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interrupt-parent = <&UIC1>;
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interrupts = <0x1e 0x4 0x1f 0x4>;
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reg = <0x40000900 0x00000074>;
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local-mac-address = [000000000000]; // Filled in by zImage
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mal-device = <&MAL0>;
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mal-tx-channel = <1>;
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mal-rx-channel = <1>;
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cell-index = <1>;
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max-frame-size = <1500>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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phy-mode = "rmii";
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phy-map = <0x00000001>;
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zmii-device = <&ZMII0>;
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zmii-channel = <1>;
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};
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EMAC2: ethernet@40000c00 {
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device_type = "network";
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compatible = "ibm,emac-440gx", "ibm,emac4";
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interrupt-parent = <&UIC2>;
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interrupts = <0x0 0x4 0x1 0x4>;
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reg = <0x40000c00 0x00000074>;
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local-mac-address = [000000000000]; // Filled in by zImage
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mal-device = <&MAL0>;
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mal-tx-channel = <2>;
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mal-rx-channel = <2>;
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cell-index = <2>;
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max-frame-size = <9000>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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phy-mode = "rgmii";
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phy-address = <1>;
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rgmii-device = <&RGMII0>;
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rgmii-channel = <0>;
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zmii-device = <&ZMII0>;
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zmii-channel = <2>;
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tah-device = <&TAH0>;
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tah-channel = <0>;
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};
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EMAC3: ethernet@40000e00 {
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device_type = "network";
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compatible = "ibm,emac-440gx", "ibm,emac4";
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interrupt-parent = <&UIC2>;
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interrupts = <0x2 0x4 0x3 0x4>;
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reg = <0x40000e00 0x00000074>;
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local-mac-address = [000000000000]; // Filled in by zImage
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mal-device = <&MAL0>;
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mal-tx-channel = <3>;
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mal-rx-channel = <3>;
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cell-index = <3>;
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max-frame-size = <9000>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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phy-mode = "rgmii";
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phy-address = <3>;
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rgmii-device = <&RGMII0>;
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rgmii-channel = <1>;
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zmii-device = <&ZMII0>;
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zmii-channel = <3>;
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tah-device = <&TAH1>;
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tah-channel = <0>;
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};
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GPT0: gpt@40000a00 {
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/* FIXME */
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reg = <0x40000a00 0x000000d4>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
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};
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};
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PCIX0: pci@20ec00000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
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primary;
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large-inbound-windows;
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enable-msi-hole;
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reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
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0x00000000 0x00000000 0x00000000 /* no IACK cycles */
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0x00000002 0x0ed00000 0x00000004 /* Special cycles */
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0x00000002 0x0ec80000 0x00000100 /* Internal registers */
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0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
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0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 1 */
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0x800 0x0 0x0 0x1 &UIC0 0x17 0x8
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0x800 0x0 0x0 0x2 &UIC0 0x18 0x8
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0x800 0x0 0x0 0x3 &UIC0 0x19 0x8
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0x800 0x0 0x0 0x4 &UIC0 0x1a 0x8
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/* IDSEL 2 */
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0x1000 0x0 0x0 0x1 &UIC0 0x18 0x8
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0x1000 0x0 0x0 0x2 &UIC0 0x19 0x8
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0x1000 0x0 0x0 0x3 &UIC0 0x1a 0x8
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0x1000 0x0 0x0 0x4 &UIC0 0x17 0x8
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>;
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};
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};
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chosen {
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linux,stdout-path = "/plb/opb/serial@40000300";
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};
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};
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