0f22aab897
This driver is for the Airgo AGNX00 wireless chip. From: Li YanBo <dreamfly281@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
651 lines
16 KiB
C
651 lines
16 KiB
C
/**
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* Airgo MIMO wireless driver
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*
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* Copyright (c) 2007 Li YanBo <dreamfly281@gmail.com>
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* Thanks for Jeff Williams <angelbane@gmail.com> do reverse engineer
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* works and published the SPECS at http://airgo.wdwconsulting.net/mymoin
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/etherdevice.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include "agnx.h"
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#include "debug.h"
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#include "xmit.h"
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#include "phy.h"
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MODULE_AUTHOR("Li YanBo <dreamfly281@gmail.com>");
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MODULE_DESCRIPTION("Airgo MIMO PCI wireless driver");
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MODULE_LICENSE("GPL");
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static struct pci_device_id agnx_pci_id_tbl[] __devinitdata = {
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{ PCI_DEVICE(0x17cb, 0x0001) }, /* Beklin F5d8010, Netgear WGM511 etc */
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{ PCI_DEVICE(0x17cb, 0x0002) }, /* Netgear Wpnt511 */
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{ 0 }
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};
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MODULE_DEVICE_TABLE(pci, agnx_pci_id_tbl);
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static inline void agnx_interrupt_ack(struct agnx_priv *priv, u32 *reason)
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{
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void __iomem *ctl = priv->ctl;
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u32 reg;
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if ( *reason & AGNX_STAT_RX ) {
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/* Mark complete RX */
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reg = ioread32(ctl + AGNX_CIR_RXCTL);
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reg |= 0x4;
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iowrite32(reg, ctl + AGNX_CIR_RXCTL);
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/* disable Rx interrupt */
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}
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if ( *reason & AGNX_STAT_TX ) {
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reg = ioread32(ctl + AGNX_CIR_TXDCTL);
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if (reg & 0x4) {
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iowrite32(reg, ctl + AGNX_CIR_TXDCTL);
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*reason |= AGNX_STAT_TXD;
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}
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reg = ioread32(ctl + AGNX_CIR_TXMCTL);
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if (reg & 0x4) {
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iowrite32(reg, ctl + AGNX_CIR_TXMCTL);
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*reason |= AGNX_STAT_TXM;
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}
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}
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if ( *reason & AGNX_STAT_X ) {
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/* reg = ioread32(ctl + AGNX_INT_STAT); */
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/* iowrite32(reg, ctl + AGNX_INT_STAT); */
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/* /\* FIXME reinit interrupt mask *\/ */
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/* reg = 0xc390bf9 & ~IRQ_TX_BEACON; */
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/* reg &= ~IRQ_TX_DISABLE; */
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/* iowrite32(reg, ctl + AGNX_INT_MASK); */
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/* iowrite32(0x800, ctl + AGNX_CIR_BLKCTL); */
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}
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} /* agnx_interrupt_ack */
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static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
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{
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struct ieee80211_hw *dev = dev_id;
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struct agnx_priv *priv = dev->priv;
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void __iomem *ctl = priv->ctl;
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irqreturn_t ret = IRQ_NONE;
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u32 irq_reason;
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spin_lock(&priv->lock);
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// printk(KERN_ERR PFX "Get a interrupt %s\n", __func__);
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if (priv->init_status != AGNX_START)
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goto out;
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/* FiXME Here has no lock, Is this will lead to race? */
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irq_reason = ioread32(ctl + AGNX_CIR_BLKCTL);
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if (!(irq_reason & 0x7))
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goto out;
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ret = IRQ_HANDLED;
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priv->irq_status = ioread32(ctl + AGNX_INT_STAT);
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// printk(PFX "Interrupt reason is 0x%x\n", irq_reason);
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/* Make sure the txm and txd flags don't conflict with other unknown
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interrupt flag, maybe is not necessary */
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irq_reason &= 0xF;
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disable_rx_interrupt(priv);
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/* TODO Make sure the card finished initialized */
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agnx_interrupt_ack(priv, &irq_reason);
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if ( irq_reason & AGNX_STAT_RX )
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handle_rx_irq(priv);
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if ( irq_reason & AGNX_STAT_TXD )
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handle_txd_irq(priv);
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if ( irq_reason & AGNX_STAT_TXM )
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handle_txm_irq(priv);
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if ( irq_reason & AGNX_STAT_X )
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handle_other_irq(priv);
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enable_rx_interrupt(priv);
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out:
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spin_unlock(&priv->lock);
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return ret;
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} /* agnx_interrupt_handler */
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/* FIXME */
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static int agnx_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
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{
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AGNX_TRACE;
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return _agnx_tx(dev->priv, skb);
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} /* agnx_tx */
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static int agnx_get_mac_address(struct agnx_priv *priv)
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{
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void __iomem *ctl = priv->ctl;
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u32 reg;
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AGNX_TRACE;
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/* Attention! directly read the MAC or other date from EEPROM will
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lead to cardbus(WGM511) lock up when write to PM PLL register */
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reg = agnx_read32(ctl, 0x3544);
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udelay(40);
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reg = agnx_read32(ctl, 0x354c);
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udelay(50);
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/* Get the mac address */
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reg = agnx_read32(ctl, 0x3544);
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udelay(40);
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/* HACK */
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reg = cpu_to_le32(reg);
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priv->mac_addr[0] = ((u8 *)®)[2];
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priv->mac_addr[1] = ((u8 *)®)[3];
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reg = agnx_read32(ctl, 0x3548);
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udelay(50);
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*((u32 *)(priv->mac_addr + 2)) = cpu_to_le32(reg);
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if (!is_valid_ether_addr(priv->mac_addr)) {
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DECLARE_MAC_BUF(mbuf);
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printk(KERN_WARNING PFX "read mac %s\n", print_mac(mbuf, priv->mac_addr));
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printk(KERN_WARNING PFX "Invalid hwaddr! Using random hwaddr\n");
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random_ether_addr(priv->mac_addr);
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}
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return 0;
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} /* agnx_get_mac_address */
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static int agnx_alloc_rings(struct agnx_priv *priv)
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{
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unsigned int len;
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AGNX_TRACE;
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/* Allocate RX/TXM/TXD rings info */
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priv->rx.size = AGNX_RX_RING_SIZE;
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priv->txm.size = AGNX_TXM_RING_SIZE;
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priv->txd.size = AGNX_TXD_RING_SIZE;
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len = priv->rx.size + priv->txm.size + priv->txd.size;
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// priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_KERNEL);
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priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_ATOMIC);
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if (!priv->rx.info)
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return -ENOMEM;
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priv->txm.info = priv->rx.info + priv->rx.size;
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priv->txd.info = priv->txm.info + priv->txm.size;
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/* Allocate RX/TXM/TXD descriptors */
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priv->rx.desc = pci_alloc_consistent(priv->pdev, sizeof(struct agnx_desc) * len,
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&priv->rx.dma);
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if (!priv->rx.desc) {
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kfree(priv->rx.info);
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return -ENOMEM;
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}
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priv->txm.desc = priv->rx.desc + priv->rx.size;
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priv->txm.dma = priv->rx.dma + sizeof(struct agnx_desc) * priv->rx.size;
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priv->txd.desc = priv->txm.desc + priv->txm.size;
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priv->txd.dma = priv->txm.dma + sizeof(struct agnx_desc) * priv->txm.size;
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return 0;
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} /* agnx_alloc_rings */
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static void rings_free(struct agnx_priv *priv)
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{
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unsigned int len = priv->rx.size + priv->txm.size + priv->txd.size;
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unsigned long flags;
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AGNX_TRACE;
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spin_lock_irqsave(&priv->lock, flags);
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kfree(priv->rx.info);
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pci_free_consistent(priv->pdev, sizeof(struct agnx_desc) * len,
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priv->rx.desc, priv->rx.dma);
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void agnx_periodic_work_handler(struct work_struct *work)
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{
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struct agnx_priv *priv = container_of(work, struct agnx_priv,
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periodic_work.work);
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// unsigned long flags;
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unsigned long delay;
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/* fixme: using mutex?? */
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// spin_lock_irqsave(&priv->lock, flags);
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/* TODO Recalibrate*/
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// calibrate_oscillator(priv);
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// antenna_calibrate(priv);
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// agnx_send_packet(priv, 997);
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/* FIXME */
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/* if (debug == 3) */
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/* delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); */
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/* else */
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delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY);
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// delay = round_jiffies(HZ * 15);
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queue_delayed_work(priv->hw->workqueue, &priv->periodic_work, delay);
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// spin_unlock_irqrestore(&priv->lock, flags);
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}
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static int agnx_start(struct ieee80211_hw *dev)
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{
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struct agnx_priv *priv = dev->priv;
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unsigned long delay;
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int err = 0;
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AGNX_TRACE;
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err = agnx_alloc_rings(priv);
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if (err) {
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printk(KERN_ERR PFX "Can't alloc RX/TXM/TXD rings\n");
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goto out;
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}
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err = request_irq(priv->pdev->irq, &agnx_interrupt_handler,
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IRQF_SHARED, "agnx_pci", dev);
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if (err) {
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printk(KERN_ERR PFX "Failed to register IRQ handler\n");
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rings_free(priv);
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goto out;
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}
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// mdelay(500);
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might_sleep();
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agnx_hw_init(priv);
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// mdelay(500);
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might_sleep();
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priv->init_status = AGNX_START;
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/* INIT_DELAYED_WORK(&priv->periodic_work, agnx_periodic_work_handler); */
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/* delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); */
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/* queue_delayed_work(priv->hw->workqueue, &priv->periodic_work, delay); */
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out:
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return err;
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} /* agnx_start */
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static void agnx_stop(struct ieee80211_hw *dev)
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{
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struct agnx_priv *priv = dev->priv;
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AGNX_TRACE;
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priv->init_status = AGNX_STOP;
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/* make sure hardware will not generate irq */
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agnx_hw_reset(priv);
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free_irq(priv->pdev->irq, dev);
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flush_workqueue(priv->hw->workqueue);
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// cancel_delayed_work_sync(&priv->periodic_work);
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unfill_rings(priv);
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rings_free(priv);
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}
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static int agnx_config(struct ieee80211_hw *dev,
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struct ieee80211_conf *conf)
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{
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struct agnx_priv *priv = dev->priv;
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int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
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AGNX_TRACE;
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spin_lock(&priv->lock);
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/* FIXME need priv lock? */
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if (channel != priv->channel) {
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priv->channel = channel;
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agnx_set_channel(priv, priv->channel);
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}
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spin_unlock(&priv->lock);
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return 0;
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}
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static int agnx_config_interface(struct ieee80211_hw *dev,
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struct ieee80211_vif *vif,
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struct ieee80211_if_conf *conf)
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{
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struct agnx_priv *priv = dev->priv;
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void __iomem *ctl = priv->ctl;
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AGNX_TRACE;
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spin_lock(&priv->lock);
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if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
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// u32 reghi, reglo;
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agnx_set_bssid(priv, conf->bssid);
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memcpy(priv->bssid, conf->bssid, ETH_ALEN);
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hash_write(priv, conf->bssid, BSSID_STAID);
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sta_init(priv, BSSID_STAID);
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/* FIXME needed? */
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sta_power_init(priv, BSSID_STAID);
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agnx_write32(ctl, AGNX_BM_MTSM, 0xff & ~0x1);
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}
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if (conf->ssid_len != priv->ssid_len ||
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memcmp(conf->ssid, priv->ssid, conf->ssid_len)) {
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agnx_set_ssid(priv, conf->ssid, conf->ssid_len);
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priv->ssid_len = conf->ssid_len;
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memcpy(priv->ssid, conf->ssid, conf->ssid_len);
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}
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spin_unlock(&priv->lock);
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return 0;
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} /* agnx_config_interface */
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static void agnx_configure_filter(struct ieee80211_hw *dev,
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unsigned int changed_flags,
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unsigned int *total_flags,
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int mc_count, struct dev_mc_list *mclist)
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{
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unsigned int new_flags = 0;
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*total_flags = new_flags;
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/* TODO */
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}
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static int agnx_add_interface(struct ieee80211_hw *dev,
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struct ieee80211_if_init_conf *conf)
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{
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struct agnx_priv *priv = dev->priv;
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AGNX_TRACE;
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spin_lock(&priv->lock);
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/* FIXME */
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if (priv->mode != NL80211_IFTYPE_MONITOR)
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return -EOPNOTSUPP;
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switch (conf->type) {
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case NL80211_IFTYPE_STATION:
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priv->mode = conf->type;
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break;
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default:
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return -EOPNOTSUPP;
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}
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spin_unlock(&priv->lock);
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return 0;
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}
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static void agnx_remove_interface(struct ieee80211_hw *dev,
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struct ieee80211_if_init_conf *conf)
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{
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struct agnx_priv *priv = dev->priv;
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AGNX_TRACE;
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/* TODO */
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priv->mode = NL80211_IFTYPE_MONITOR;
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}
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static int agnx_get_stats(struct ieee80211_hw *dev,
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struct ieee80211_low_level_stats *stats)
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{
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struct agnx_priv *priv = dev->priv;
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AGNX_TRACE;
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spin_lock(&priv->lock);
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/* TODO !! */
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memcpy(stats, &priv->stats, sizeof(*stats));
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spin_unlock(&priv->lock);
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return 0;
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}
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static u64 agnx_get_tsft(struct ieee80211_hw *dev)
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{
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void __iomem *ctl = ((struct agnx_priv *)dev->priv)->ctl;
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u32 tsftl;
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u64 tsft;
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AGNX_TRACE;
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/* FIXME */
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tsftl = ioread32(ctl + AGNX_TXM_TIMESTAMPLO);
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tsft = ioread32(ctl + AGNX_TXM_TIMESTAMPHI);
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tsft <<= 32;
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tsft |= tsftl;
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return tsft;
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}
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static int agnx_get_tx_stats(struct ieee80211_hw *dev,
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struct ieee80211_tx_queue_stats *stats)
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{
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struct agnx_priv *priv = dev->priv;
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AGNX_TRACE;
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/* FIXME now we just using txd queue, but should using txm queue too */
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stats[0].len = (priv->txd.idx - priv->txd.idx_sent) / 2;
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stats[0].limit = priv->txd.size - 2;
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stats[0].count = priv->txd.idx / 2;
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return 0;
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}
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static struct ieee80211_ops agnx_ops = {
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.tx = agnx_tx,
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.start = agnx_start,
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.stop = agnx_stop,
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.add_interface = agnx_add_interface,
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.remove_interface = agnx_remove_interface,
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.config = agnx_config,
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.config_interface = agnx_config_interface,
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.configure_filter = agnx_configure_filter,
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.get_stats = agnx_get_stats,
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.get_tx_stats = agnx_get_tx_stats,
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.get_tsf = agnx_get_tsft
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};
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static void __devexit agnx_pci_remove(struct pci_dev *pdev)
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{
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struct ieee80211_hw *dev = pci_get_drvdata(pdev);
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struct agnx_priv *priv = dev->priv;
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AGNX_TRACE;
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if (!dev)
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return;
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ieee80211_unregister_hw(dev);
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pci_iounmap(pdev, priv->ctl);
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pci_iounmap(pdev, priv->data);
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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ieee80211_free_hw(dev);
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}
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static int __devinit agnx_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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struct ieee80211_hw *dev;
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struct agnx_priv *priv;
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u32 mem_addr0, mem_len0;
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u32 mem_addr1, mem_len1;
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int err;
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DECLARE_MAC_BUF(mac);
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err = pci_enable_device(pdev);
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if (err) {
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printk(KERN_ERR PFX "Can't enable new PCI device\n");
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return err;
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}
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/* get pci resource */
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mem_addr0 = pci_resource_start(pdev, 0);
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mem_len0 = pci_resource_len(pdev, 0);
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mem_addr1 = pci_resource_start(pdev, 1);
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mem_len1 = pci_resource_len(pdev, 1);
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printk(KERN_DEBUG PFX "Memaddr0 is %x, length is %x\n", mem_addr0, mem_len0);
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printk(KERN_DEBUG PFX "Memaddr1 is %x, length is %x\n", mem_addr1, mem_len1);
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err = pci_request_regions(pdev, "agnx-pci");
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if (err) {
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printk(KERN_ERR PFX "Can't obtain PCI resource\n");
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return err;
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}
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if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
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pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
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printk(KERN_ERR PFX "No suitable DMA available\n");
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goto err_free_reg;
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}
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|
|
pci_set_master(pdev);
|
|
printk(KERN_DEBUG PFX "pdev->irq is %d\n", pdev->irq);
|
|
|
|
dev = ieee80211_alloc_hw(sizeof(*priv), &agnx_ops);
|
|
if (!dev) {
|
|
printk(KERN_ERR PFX "ieee80211 alloc failed\n");
|
|
err = -ENOMEM;
|
|
goto err_free_reg;
|
|
}
|
|
/* init priv */
|
|
priv = dev->priv;
|
|
memset(priv, 0, sizeof(*priv));
|
|
priv->mode = NL80211_IFTYPE_MONITOR;
|
|
priv->pdev = pdev;
|
|
priv->hw = dev;
|
|
spin_lock_init(&priv->lock);
|
|
priv->init_status = AGNX_UNINIT;
|
|
|
|
/* Map mem #1 and #2 */
|
|
priv->ctl = pci_iomap(pdev, 0, mem_len0);
|
|
// printk(KERN_DEBUG PFX"MEM1 mapped address is 0x%p\n", priv->ctl);
|
|
if (!priv->ctl) {
|
|
printk(KERN_ERR PFX "Can't map device memory\n");
|
|
goto err_free_dev;
|
|
}
|
|
priv->data = pci_iomap(pdev, 1, mem_len1);
|
|
printk(KERN_DEBUG PFX "MEM2 mapped address is 0x%p\n", priv->data);
|
|
if (!priv->data) {
|
|
printk(KERN_ERR PFX "Can't map device memory\n");
|
|
goto err_iounmap2;
|
|
}
|
|
|
|
pci_read_config_byte(pdev, PCI_REVISION_ID, &priv->revid);
|
|
|
|
priv->band.channels = (struct ieee80211_channel *)agnx_channels;
|
|
priv->band.n_channels = ARRAY_SIZE(agnx_channels);
|
|
priv->band.bitrates = (struct ieee80211_rate *)agnx_rates_80211g;
|
|
priv->band.n_bitrates = ARRAY_SIZE(agnx_rates_80211g);
|
|
|
|
/* Init ieee802.11 dev */
|
|
SET_IEEE80211_DEV(dev, &pdev->dev);
|
|
pci_set_drvdata(pdev, dev);
|
|
dev->extra_tx_headroom = sizeof(struct agnx_hdr);
|
|
|
|
/* FIXME It only include FCS in promious mode but not manage mode */
|
|
/* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS; */
|
|
dev->channel_change_time = 5000;
|
|
dev->max_signal = 100;
|
|
/* FIXME */
|
|
dev->queues = 1;
|
|
|
|
agnx_get_mac_address(priv);
|
|
|
|
SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
|
|
|
|
/* /\* FIXME *\/ */
|
|
/* for (i = 1; i < NUM_DRIVE_MODES; i++) { */
|
|
/* err = ieee80211_register_hwmode(dev, &priv->modes[i]); */
|
|
/* if (err) { */
|
|
/* printk(KERN_ERR PFX "Can't register hwmode\n"); */
|
|
/* goto err_iounmap; */
|
|
/* } */
|
|
/* } */
|
|
|
|
priv->channel = 1;
|
|
dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
|
|
|
|
err = ieee80211_register_hw(dev);
|
|
if (err) {
|
|
printk(KERN_ERR PFX "Can't register hardware\n");
|
|
goto err_iounmap;
|
|
}
|
|
|
|
agnx_hw_reset(priv);
|
|
|
|
|
|
printk(PFX "%s: hwaddr %s, Rev 0x%02x\n", wiphy_name(dev->wiphy),
|
|
print_mac(mac, dev->wiphy->perm_addr), priv->revid);
|
|
return 0;
|
|
|
|
err_iounmap:
|
|
pci_iounmap(pdev, priv->data);
|
|
|
|
err_iounmap2:
|
|
pci_iounmap(pdev, priv->ctl);
|
|
|
|
err_free_dev:
|
|
pci_set_drvdata(pdev, NULL);
|
|
ieee80211_free_hw(dev);
|
|
|
|
err_free_reg:
|
|
pci_release_regions(pdev);
|
|
|
|
pci_disable_device(pdev);
|
|
return err;
|
|
} /* agnx_pci_probe*/
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int agnx_pci_suspend(struct pci_dev *pdev, pm_message_t state)
|
|
{
|
|
struct ieee80211_hw *dev = pci_get_drvdata(pdev);
|
|
AGNX_TRACE;
|
|
|
|
ieee80211_stop_queues(dev);
|
|
agnx_stop(dev);
|
|
|
|
pci_save_state(pdev);
|
|
pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
|
return 0;
|
|
}
|
|
|
|
static int agnx_pci_resume(struct pci_dev *pdev)
|
|
{
|
|
struct ieee80211_hw *dev = pci_get_drvdata(pdev);
|
|
AGNX_TRACE;
|
|
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
pci_restore_state(pdev);
|
|
|
|
agnx_start(dev);
|
|
ieee80211_wake_queues(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
|
|
#define agnx_pci_suspend NULL
|
|
#define agnx_pci_resume NULL
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
|
|
static struct pci_driver agnx_pci_driver = {
|
|
.name = "agnx-pci",
|
|
.id_table = agnx_pci_id_tbl,
|
|
.probe = agnx_pci_probe,
|
|
.remove = __devexit_p(agnx_pci_remove),
|
|
.suspend = agnx_pci_suspend,
|
|
.resume = agnx_pci_resume,
|
|
};
|
|
|
|
static int __init agnx_pci_init(void)
|
|
{
|
|
AGNX_TRACE;
|
|
return pci_register_driver(&agnx_pci_driver);
|
|
}
|
|
|
|
static void __exit agnx_pci_exit(void)
|
|
{
|
|
AGNX_TRACE;
|
|
pci_unregister_driver(&agnx_pci_driver);
|
|
}
|
|
|
|
|
|
module_init(agnx_pci_init);
|
|
module_exit(agnx_pci_exit);
|