a5d411962c
Amlogic Meson GX SoCs (GXL and AXG) come with a (host-only) dwc3 USB controller. This requires a clock to be enabled and a reset line to be pulsed to get the hardware into a known state. Add the documentation for this IP block, similar to "qcom,dwc3.txt". Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
43 lines
1.3 KiB
Plaintext
43 lines
1.3 KiB
Plaintext
Amlogic Meson GX DWC3 USB SoC controller
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Required properties:
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- compatible: depending on the SoC this should contain one of:
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* amlogic,meson-axg-dwc3
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* amlogic,meson-gxl-dwc3
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- clocks: a handle for the "USB general" clock
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- clock-names: must be "usb_general"
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- resets: a handle for the shared "USB OTG" reset line
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- reset-names: must be "usb_otg"
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Required child node:
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A child node must exist to represent the core DWC3 IP block. The name of
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the node is not important. The content of the node is defined in dwc3.txt.
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PHY documentation is provided in the following places:
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- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt
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- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt
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Example device nodes:
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usb0: usb@ff500000 {
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compatible = "amlogic,meson-axg-dwc3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&clkc CLKID_USB>;
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clock-names = "usb_general";
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resets = <&reset RESET_USB_OTG>;
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reset-names = "usb_otg";
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dwc3: dwc3@ff500000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xff500000 0x0 0x100000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "host";
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maximum-speed = "high-speed";
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snps,dis_u2_susphy_quirk;
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phys = <&usb3_phy>, <&usb2_phy0>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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