497c8b6096
This patch introduces the support for Keymile's kmcoge4 board which is the internal reference design for boards based on Freescale's P2040/P2041 SoCs. This internal reference design is named kmp204x. The peripherals used on this board are: - SPI NOR Flash as bootloader medium - NAND Flash with a ubi partition - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 4 Local Bus windows, with one dedicated to the QRIO reset/power mgmt CPLD - 2 I2C busses - last but not least, the mandatory serial port The patch also adds a defconfig file for this reference design that is necessary because of the lowmem option that must be set higher due to the number of PCIe devices with big ioremapped mem ranges on the boad. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
153 lines
3.1 KiB
Plaintext
153 lines
3.1 KiB
Plaintext
/*
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* Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
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*
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* (C) Copyright 2014
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* Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "fsl/p2041si-pre.dtsi"
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/ {
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model = "keymile,kmcoge4";
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compatible = "keymile,kmcoge4", "keymile,kmp204x";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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memory {
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device_type = "memory";
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};
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dcsr: dcsr@f00000000 {
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ranges = <0x00000000 0xf 0x00000000 0x01008000>;
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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spi@110000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25fl256s1";
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reg = <0>;
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spi-max-frequency = <20000000>; /* input clock */
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};
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network_clock@1 {
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compatible = "zarlink,zl30343";
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reg = <1>;
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spi-max-frequency = <8000000>;
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};
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flash@2 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,m25p32";
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reg = <2>;
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spi-max-frequency = <15000000>;
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};
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};
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i2c@119000 {
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status = "disabled";
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};
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i2c@119100 {
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status = "disabled";
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};
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usb0: usb@210000 {
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status = "disabled";
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};
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usb1: usb@211000 {
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status = "disabled";
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};
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sata@220000 {
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status = "disabled";
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};
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sata@221000 {
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status = "disabled";
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};
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};
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rio: rapidio@ffe0c0000 {
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status = "disabled";
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};
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lbc: localbus@ffe124000 {
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reg = <0xf 0xfe124000 0 0x1000>;
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ranges = <0 0 0xf 0xffa00000 0x00040000 /* LB 0 */
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1 0 0xf 0xfb000000 0x00010000 /* LB 1 */
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2 0 0xf 0xd0000000 0x10000000 /* LB 2 */
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3 0 0xf 0xe0000000 0x10000000>; /* LB 3 */
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nand@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,elbc-fcm-nand";
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reg = <0 0 0x40000>;
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};
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board-control@1,0 {
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compatible = "keymile,qriox";
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reg = <1 0 0x80>;
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};
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chassis-mgmt@3,0 {
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compatible = "keymile,bfticu";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <3 0 0x100>;
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interrupt-parent = <&mpic>;
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interrupts = <6 1 0 0>;
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};
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};
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pci0: pcie@ffe200000 {
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reg = <0xf 0xfe200000 0 0x1000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
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0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci1: pcie@ffe201000 {
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status = "disabled";
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};
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pci2: pcie@ffe202000 {
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reg = <0xf 0xfe202000 0 0x1000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
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0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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};
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/include/ "fsl/p2041si-post.dtsi"
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