Suzuki K Poulose 0bbb194c0c coresight: Extend the PIDR mask to cover relevant bits in PIDR2 ... As per coresight standards, PIDR2 register has the following format : [2-0] - JEP106_bits6to4 [3] - JEDEC, designer ID is specified by JEDEC. However some of the drivers only use mask of 0x3 for the PIDR2 leaving bits [3-2] unchecked, which could potentially match the component for a different device altogether. This patch fixes the mask and the corresponding id bits for the existing devices. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2017-10-20 15:03:06 +02:00
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coresight	coresight: Extend the PIDR mask to cover relevant bits in PIDR2	2017-10-20 15:03:06 +02:00
intel_th	intel_th: pci: Add Lewisburg PCH support	2017-09-22 10:28:00 +02:00
stm	stm class: Fix a use-after-free	2017-09-22 10:28:00 +02:00