6656920b0b
Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net>
199 lines
5.6 KiB
C
199 lines
5.6 KiB
C
/*
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* include/asm-xtensa/io.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_IO_H
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#define _XTENSA_IO_H
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#ifdef __KERNEL__
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#include <asm/byteorder.h>
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#include <asm/page.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#define XCHAL_KIO_CACHED_VADDR 0xf0000000
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#define XCHAL_KIO_BYPASS_VADDR 0xf8000000
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#define XCHAL_KIO_PADDR 0xf0000000
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#define XCHAL_KIO_SIZE 0x08000000
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/*
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* swap functions to change byte order from little-endian to big-endian and
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* vice versa.
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*/
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static inline unsigned short _swapw (unsigned short v)
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{
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return (v << 8) | (v >> 8);
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}
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static inline unsigned int _swapl (unsigned int v)
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{
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return (v << 24) | ((v & 0xff00) << 8) | ((v >> 8) & 0xff00) | (v >> 24);
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}
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/*
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* Change virtual addresses to physical addresses and vv.
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* These are trivial on the 1:1 Linux/Xtensa mapping
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*/
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static inline unsigned long virt_to_phys(volatile void * address)
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{
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return __pa(address);
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}
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static inline void * phys_to_virt(unsigned long address)
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{
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return __va(address);
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}
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/*
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* virt_to_bus and bus_to_virt are deprecated.
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*/
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#define virt_to_bus(x) virt_to_phys(x)
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#define bus_to_virt(x) phys_to_virt(x)
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/*
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* Return the virtual (cached) address for the specified bus memory.
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* Note that we currently don't support any address outside the KIO segment.
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*/
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static inline void *ioremap(unsigned long offset, unsigned long size)
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{
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if (offset >= XCHAL_KIO_PADDR
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&& offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE)
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return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR);
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else
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BUG();
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}
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static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
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{
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if (offset >= XCHAL_KIO_PADDR
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&& offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE)
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return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR);
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else
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BUG();
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}
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static inline void iounmap(void *addr)
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{
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}
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/*
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* Generic I/O
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*/
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#define readb(addr) \
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({ unsigned char __v = (*(volatile unsigned char *)(addr)); __v; })
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#define readw(addr) \
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({ unsigned short __v = (*(volatile unsigned short *)(addr)); __v; })
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#define readl(addr) \
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({ unsigned int __v = (*(volatile unsigned int *)(addr)); __v; })
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#define writeb(b, addr) (void)((*(volatile unsigned char *)(addr)) = (b))
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#define writew(b, addr) (void)((*(volatile unsigned short *)(addr)) = (b))
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#define writel(b, addr) (void)((*(volatile unsigned int *)(addr)) = (b))
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static inline __u8 __raw_readb(const volatile void __iomem *addr)
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{
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return *(__force volatile __u8 *)(addr);
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}
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static inline __u16 __raw_readw(const volatile void __iomem *addr)
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{
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return *(__force volatile __u16 *)(addr);
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}
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static inline __u32 __raw_readl(const volatile void __iomem *addr)
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{
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return *(__force volatile __u32 *)(addr);
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}
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static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
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{
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*(__force volatile __u8 *)(addr) = b;
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}
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static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
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{
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*(__force volatile __u16 *)(addr) = b;
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}
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static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
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{
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*(__force volatile __u32 *)(addr) = b;
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}
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/* These are the definitions for the x86 IO instructions
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* inb/inw/inl/outb/outw/outl, the "string" versions
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* insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions
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* inb_p/inw_p/...
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* The macros don't do byte-swapping.
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*/
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#define inb(port) readb((u8 *)((port)))
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#define outb(val, port) writeb((val),(u8 *)((unsigned long)(port)))
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#define inw(port) readw((u16 *)((port)))
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#define outw(val, port) writew((val),(u16 *)((unsigned long)(port)))
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#define inl(port) readl((u32 *)((port)))
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#define outl(val, port) writel((val),(u32 *)((unsigned long)(port)))
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#define inb_p(port) inb((port))
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#define outb_p(val, port) outb((val), (port))
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#define inw_p(port) inw((port))
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#define outw_p(val, port) outw((val), (port))
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#define inl_p(port) inl((port))
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#define outl_p(val, port) outl((val), (port))
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extern void insb (unsigned long port, void *dst, unsigned long count);
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extern void insw (unsigned long port, void *dst, unsigned long count);
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extern void insl (unsigned long port, void *dst, unsigned long count);
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extern void outsb (unsigned long port, const void *src, unsigned long count);
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extern void outsw (unsigned long port, const void *src, unsigned long count);
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extern void outsl (unsigned long port, const void *src, unsigned long count);
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#define IO_SPACE_LIMIT ~0
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#define memset_io(a,b,c) memset((void *)(a),(b),(c))
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#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
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#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
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/* At this point the Xtensa doesn't provide byte swap instructions */
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#ifdef __XTENSA_EB__
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# define in_8(addr) (*(u8*)(addr))
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# define in_le16(addr) _swapw(*(u16*)(addr))
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# define in_le32(addr) _swapl(*(u32*)(addr))
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# define out_8(b, addr) *(u8*)(addr) = (b)
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# define out_le16(b, addr) *(u16*)(addr) = _swapw(b)
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# define out_le32(b, addr) *(u32*)(addr) = _swapl(b)
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#elif defined(__XTENSA_EL__)
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# define in_8(addr) (*(u8*)(addr))
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# define in_le16(addr) (*(u16*)(addr))
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# define in_le32(addr) (*(u32*)(addr))
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# define out_8(b, addr) *(u8*)(addr) = (b)
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# define out_le16(b, addr) *(u16*)(addr) = (b)
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# define out_le32(b, addr) *(u32*)(addr) = (b)
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#else
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# error processor byte order undefined!
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#endif
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_IO_H */
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