0895ecda79
The hugepage arch code provides a number of hook functions/macros which mirror the functionality of various normal page pte access functions. Various changes in the normal page accessors (in particular BenH's recent changes to the handling of lazy icache flushing and PAGE_EXEC) have caused the hugepage versions to get out of sync with the originals. In some cases, this is a bug, at least on some MMU types. One of the reasons that some hooks were not identical to the normal page versions, is that the fact we're dealing with a hugepage needed to be passed down do use the correct dcache-icache flush function. This patch makes the main flush_dcache_icache_page() function hugepage aware (by checking for the PageCompound flag). That in turn means we can make set_huge_pte_at() just a call to set_pte_at() bringing it back into sync. As a bonus, this lets us remove the hash_huge_page_do_lazy_icache() function, replacing it with a call to the hash_page_do_lazy_icache() function it was based on. Some other hugepage pte access hooks - huge_ptep_get_and_clear() and huge_ptep_clear_flush() - are not so easily unified, but this patch at least brings them back into sync with the current versions of the corresponding normal page functions. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
1221 lines
32 KiB
C
1221 lines
32 KiB
C
/*
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* PowerPC64 port by Mike Corrigan and Dave Engebretsen
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* {mikejc|engebret}@us.ibm.com
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*
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* Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
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*
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* SMP scalability work:
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* Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* Module name: htab.c
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*
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* Description:
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* PowerPC Hashed Page Table functions
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#undef DEBUG_LOW
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/stat.h>
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#include <linux/sysctl.h>
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#include <linux/ctype.h>
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#include <linux/cache.h>
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#include <linux/init.h>
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#include <linux/signal.h>
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#include <linux/lmb.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/system.h>
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#include <asm/uaccess.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/abs_addr.h>
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#include <asm/tlbflush.h>
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#include <asm/io.h>
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#include <asm/eeh.h>
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#include <asm/tlb.h>
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#include <asm/cacheflush.h>
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#include <asm/cputable.h>
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#include <asm/sections.h>
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#include <asm/spu.h>
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#include <asm/udbg.h>
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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#ifdef DEBUG_LOW
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#define DBG_LOW(fmt...) udbg_printf(fmt)
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#else
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#define DBG_LOW(fmt...)
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#endif
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#define KB (1024)
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#define MB (1024*KB)
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#define GB (1024L*MB)
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/*
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* Note: pte --> Linux PTE
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* HPTE --> PowerPC Hashed Page Table Entry
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*
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* Execution context:
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* htab_initialize is called with the MMU off (of course), but
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* the kernel has been copied down to zero so it can directly
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* reference global data. At this point it is very difficult
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* to print debug info.
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*
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*/
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#ifdef CONFIG_U3_DART
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extern unsigned long dart_tablebase;
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#endif /* CONFIG_U3_DART */
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static unsigned long _SDR1;
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struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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struct hash_pte *htab_address;
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unsigned long htab_size_bytes;
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unsigned long htab_hash_mask;
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int mmu_linear_psize = MMU_PAGE_4K;
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int mmu_virtual_psize = MMU_PAGE_4K;
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int mmu_vmalloc_psize = MMU_PAGE_4K;
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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int mmu_vmemmap_psize = MMU_PAGE_4K;
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#endif
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int mmu_io_psize = MMU_PAGE_4K;
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int mmu_kernel_ssize = MMU_SEGSIZE_256M;
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int mmu_highuser_ssize = MMU_SEGSIZE_256M;
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u16 mmu_slb_size = 64;
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#ifdef CONFIG_HUGETLB_PAGE
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unsigned int HPAGE_SHIFT;
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#endif
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#ifdef CONFIG_PPC_64K_PAGES
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int mmu_ci_restrictions;
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#endif
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#ifdef CONFIG_DEBUG_PAGEALLOC
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static u8 *linear_map_hash_slots;
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static unsigned long linear_map_hash_count;
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static DEFINE_SPINLOCK(linear_map_hash_lock);
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#endif /* CONFIG_DEBUG_PAGEALLOC */
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/* There are definitions of page sizes arrays to be used when none
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* is provided by the firmware.
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*/
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/* Pre-POWER4 CPUs (4k pages only)
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*/
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static struct mmu_psize_def mmu_psize_defaults_old[] = {
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[MMU_PAGE_4K] = {
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.shift = 12,
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.sllp = 0,
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.penc = 0,
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.avpnm = 0,
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.tlbiel = 0,
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},
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};
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/* POWER4, GPUL, POWER5
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*
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* Support for 16Mb large pages
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*/
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static struct mmu_psize_def mmu_psize_defaults_gp[] = {
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[MMU_PAGE_4K] = {
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.shift = 12,
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.sllp = 0,
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.penc = 0,
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.avpnm = 0,
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.tlbiel = 1,
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},
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[MMU_PAGE_16M] = {
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.shift = 24,
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.sllp = SLB_VSID_L,
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.penc = 0,
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.avpnm = 0x1UL,
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.tlbiel = 0,
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},
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};
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static unsigned long htab_convert_pte_flags(unsigned long pteflags)
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{
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unsigned long rflags = pteflags & 0x1fa;
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/* _PAGE_EXEC -> NOEXEC */
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if ((pteflags & _PAGE_EXEC) == 0)
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rflags |= HPTE_R_N;
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/* PP bits. PAGE_USER is already PP bit 0x2, so we only
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* need to add in 0x1 if it's a read-only user page
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*/
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if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
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(pteflags & _PAGE_DIRTY)))
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rflags |= 1;
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/* Always add C */
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return rflags | HPTE_R_C;
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}
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int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
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unsigned long pstart, unsigned long prot,
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int psize, int ssize)
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{
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unsigned long vaddr, paddr;
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unsigned int step, shift;
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int ret = 0;
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shift = mmu_psize_defs[psize].shift;
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step = 1 << shift;
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prot = htab_convert_pte_flags(prot);
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DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
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vstart, vend, pstart, prot, psize, ssize);
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for (vaddr = vstart, paddr = pstart; vaddr < vend;
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vaddr += step, paddr += step) {
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unsigned long hash, hpteg;
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unsigned long vsid = get_kernel_vsid(vaddr, ssize);
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unsigned long va = hpt_va(vaddr, vsid, ssize);
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unsigned long tprot = prot;
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/* Make kernel text executable */
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if (overlaps_kernel_text(vaddr, vaddr + step))
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tprot &= ~HPTE_R_N;
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hash = hpt_hash(va, shift, ssize);
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hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
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BUG_ON(!ppc_md.hpte_insert);
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ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
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HPTE_V_BOLTED, psize, ssize);
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if (ret < 0)
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break;
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#ifdef CONFIG_DEBUG_PAGEALLOC
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if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
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linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
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#endif /* CONFIG_DEBUG_PAGEALLOC */
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}
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return ret < 0 ? ret : 0;
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}
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#ifdef CONFIG_MEMORY_HOTPLUG
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static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
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int psize, int ssize)
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{
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unsigned long vaddr;
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unsigned int step, shift;
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shift = mmu_psize_defs[psize].shift;
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step = 1 << shift;
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if (!ppc_md.hpte_removebolted) {
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printk(KERN_WARNING "Platform doesn't implement "
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"hpte_removebolted\n");
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return -EINVAL;
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}
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for (vaddr = vstart; vaddr < vend; vaddr += step)
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ppc_md.hpte_removebolted(vaddr, psize, ssize);
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return 0;
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}
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#endif /* CONFIG_MEMORY_HOTPLUG */
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static int __init htab_dt_scan_seg_sizes(unsigned long node,
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const char *uname, int depth,
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void *data)
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{
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char *type = of_get_flat_dt_prop(node, "device_type", NULL);
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u32 *prop;
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unsigned long size = 0;
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/* We are scanning "cpu" nodes only */
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if (type == NULL || strcmp(type, "cpu") != 0)
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return 0;
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prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
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&size);
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if (prop == NULL)
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return 0;
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for (; size >= 4; size -= 4, ++prop) {
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if (prop[0] == 40) {
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DBG("1T segment support detected\n");
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cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
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return 1;
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}
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}
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cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
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return 0;
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}
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static void __init htab_init_seg_sizes(void)
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{
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of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
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}
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static int __init htab_dt_scan_page_sizes(unsigned long node,
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const char *uname, int depth,
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void *data)
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{
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char *type = of_get_flat_dt_prop(node, "device_type", NULL);
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u32 *prop;
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unsigned long size = 0;
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/* We are scanning "cpu" nodes only */
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if (type == NULL || strcmp(type, "cpu") != 0)
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return 0;
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prop = (u32 *)of_get_flat_dt_prop(node,
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"ibm,segment-page-sizes", &size);
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if (prop != NULL) {
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DBG("Page sizes from device-tree:\n");
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size /= 4;
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cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
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while(size > 0) {
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unsigned int shift = prop[0];
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unsigned int slbenc = prop[1];
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unsigned int lpnum = prop[2];
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unsigned int lpenc = 0;
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struct mmu_psize_def *def;
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int idx = -1;
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size -= 3; prop += 3;
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while(size > 0 && lpnum) {
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if (prop[0] == shift)
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lpenc = prop[1];
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prop += 2; size -= 2;
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lpnum--;
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}
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switch(shift) {
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case 0xc:
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idx = MMU_PAGE_4K;
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break;
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case 0x10:
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idx = MMU_PAGE_64K;
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break;
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case 0x14:
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idx = MMU_PAGE_1M;
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break;
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case 0x18:
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idx = MMU_PAGE_16M;
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cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
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break;
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case 0x22:
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idx = MMU_PAGE_16G;
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break;
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}
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if (idx < 0)
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continue;
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def = &mmu_psize_defs[idx];
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def->shift = shift;
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if (shift <= 23)
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def->avpnm = 0;
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else
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def->avpnm = (1 << (shift - 23)) - 1;
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def->sllp = slbenc;
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def->penc = lpenc;
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/* We don't know for sure what's up with tlbiel, so
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* for now we only set it for 4K and 64K pages
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*/
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if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
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def->tlbiel = 1;
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else
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def->tlbiel = 0;
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DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
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"tlbiel=%d, penc=%d\n",
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idx, shift, def->sllp, def->avpnm, def->tlbiel,
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def->penc);
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}
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return 1;
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}
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return 0;
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}
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#ifdef CONFIG_HUGETLB_PAGE
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/* Scan for 16G memory blocks that have been set aside for huge pages
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* and reserve those blocks for 16G huge pages.
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*/
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static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
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const char *uname, int depth,
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void *data) {
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char *type = of_get_flat_dt_prop(node, "device_type", NULL);
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unsigned long *addr_prop;
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u32 *page_count_prop;
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unsigned int expected_pages;
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long unsigned int phys_addr;
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long unsigned int block_size;
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/* We are scanning "memory" nodes only */
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if (type == NULL || strcmp(type, "memory") != 0)
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return 0;
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/* This property is the log base 2 of the number of virtual pages that
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* will represent this memory block. */
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page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
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if (page_count_prop == NULL)
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return 0;
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expected_pages = (1 << page_count_prop[0]);
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addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
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if (addr_prop == NULL)
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return 0;
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phys_addr = addr_prop[0];
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block_size = addr_prop[1];
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if (block_size != (16 * GB))
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return 0;
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printk(KERN_INFO "Huge page(16GB) memory: "
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"addr = 0x%lX size = 0x%lX pages = %d\n",
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phys_addr, block_size, expected_pages);
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if (phys_addr + (16 * GB) <= lmb_end_of_DRAM()) {
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lmb_reserve(phys_addr, block_size * expected_pages);
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add_gpage(phys_addr, block_size, expected_pages);
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}
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return 0;
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}
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#endif /* CONFIG_HUGETLB_PAGE */
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static void __init htab_init_page_sizes(void)
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{
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int rc;
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/* Default to 4K pages only */
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memcpy(mmu_psize_defs, mmu_psize_defaults_old,
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sizeof(mmu_psize_defaults_old));
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/*
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* Try to find the available page sizes in the device-tree
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*/
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rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
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if (rc != 0) /* Found */
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goto found;
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/*
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* Not in the device-tree, let's fallback on known size
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* list for 16M capable GP & GR
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*/
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if (cpu_has_feature(CPU_FTR_16M_PAGE))
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memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
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sizeof(mmu_psize_defaults_gp));
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found:
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#ifndef CONFIG_DEBUG_PAGEALLOC
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/*
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* Pick a size for the linear mapping. Currently, we only support
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* 16M, 1M and 4K which is the default
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*/
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if (mmu_psize_defs[MMU_PAGE_16M].shift)
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mmu_linear_psize = MMU_PAGE_16M;
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else if (mmu_psize_defs[MMU_PAGE_1M].shift)
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mmu_linear_psize = MMU_PAGE_1M;
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#endif /* CONFIG_DEBUG_PAGEALLOC */
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#ifdef CONFIG_PPC_64K_PAGES
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/*
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* Pick a size for the ordinary pages. Default is 4K, we support
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* 64K for user mappings and vmalloc if supported by the processor.
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* We only use 64k for ioremap if the processor
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* (and firmware) support cache-inhibited large pages.
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* If not, we use 4k and set mmu_ci_restrictions so that
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* hash_page knows to switch processes that use cache-inhibited
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* mappings to 4k pages.
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*/
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if (mmu_psize_defs[MMU_PAGE_64K].shift) {
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mmu_virtual_psize = MMU_PAGE_64K;
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mmu_vmalloc_psize = MMU_PAGE_64K;
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if (mmu_linear_psize == MMU_PAGE_4K)
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mmu_linear_psize = MMU_PAGE_64K;
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if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
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/*
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* Don't use 64k pages for ioremap on pSeries, since
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* that would stop us accessing the HEA ethernet.
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*/
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if (!machine_is(pseries))
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mmu_io_psize = MMU_PAGE_64K;
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} else
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mmu_ci_restrictions = 1;
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}
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#endif /* CONFIG_PPC_64K_PAGES */
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|
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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/* We try to use 16M pages for vmemmap if that is supported
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* and we have at least 1G of RAM at boot
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*/
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if (mmu_psize_defs[MMU_PAGE_16M].shift &&
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lmb_phys_mem_size() >= 0x40000000)
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mmu_vmemmap_psize = MMU_PAGE_16M;
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else if (mmu_psize_defs[MMU_PAGE_64K].shift)
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mmu_vmemmap_psize = MMU_PAGE_64K;
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else
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mmu_vmemmap_psize = MMU_PAGE_4K;
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#endif /* CONFIG_SPARSEMEM_VMEMMAP */
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printk(KERN_DEBUG "Page orders: linear mapping = %d, "
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"virtual = %d, io = %d"
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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", vmemmap = %d"
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#endif
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"\n",
|
|
mmu_psize_defs[mmu_linear_psize].shift,
|
|
mmu_psize_defs[mmu_virtual_psize].shift,
|
|
mmu_psize_defs[mmu_io_psize].shift
|
|
#ifdef CONFIG_SPARSEMEM_VMEMMAP
|
|
,mmu_psize_defs[mmu_vmemmap_psize].shift
|
|
#endif
|
|
);
|
|
|
|
#ifdef CONFIG_HUGETLB_PAGE
|
|
/* Reserve 16G huge page memory sections for huge pages */
|
|
of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
|
|
#endif /* CONFIG_HUGETLB_PAGE */
|
|
}
|
|
|
|
static int __init htab_dt_scan_pftsize(unsigned long node,
|
|
const char *uname, int depth,
|
|
void *data)
|
|
{
|
|
char *type = of_get_flat_dt_prop(node, "device_type", NULL);
|
|
u32 *prop;
|
|
|
|
/* We are scanning "cpu" nodes only */
|
|
if (type == NULL || strcmp(type, "cpu") != 0)
|
|
return 0;
|
|
|
|
prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
|
|
if (prop != NULL) {
|
|
/* pft_size[0] is the NUMA CEC cookie */
|
|
ppc64_pft_size = prop[1];
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long __init htab_get_table_size(void)
|
|
{
|
|
unsigned long mem_size, rnd_mem_size, pteg_count, psize;
|
|
|
|
/* If hash size isn't already provided by the platform, we try to
|
|
* retrieve it from the device-tree. If it's not there neither, we
|
|
* calculate it now based on the total RAM size
|
|
*/
|
|
if (ppc64_pft_size == 0)
|
|
of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
|
|
if (ppc64_pft_size)
|
|
return 1UL << ppc64_pft_size;
|
|
|
|
/* round mem_size up to next power of 2 */
|
|
mem_size = lmb_phys_mem_size();
|
|
rnd_mem_size = 1UL << __ilog2(mem_size);
|
|
if (rnd_mem_size < mem_size)
|
|
rnd_mem_size <<= 1;
|
|
|
|
/* # pages / 2 */
|
|
psize = mmu_psize_defs[mmu_virtual_psize].shift;
|
|
pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
|
|
|
|
return pteg_count << 7;
|
|
}
|
|
|
|
#ifdef CONFIG_MEMORY_HOTPLUG
|
|
void create_section_mapping(unsigned long start, unsigned long end)
|
|
{
|
|
BUG_ON(htab_bolt_mapping(start, end, __pa(start),
|
|
pgprot_val(PAGE_KERNEL), mmu_linear_psize,
|
|
mmu_kernel_ssize));
|
|
}
|
|
|
|
int remove_section_mapping(unsigned long start, unsigned long end)
|
|
{
|
|
return htab_remove_mapping(start, end, mmu_linear_psize,
|
|
mmu_kernel_ssize);
|
|
}
|
|
#endif /* CONFIG_MEMORY_HOTPLUG */
|
|
|
|
static inline void make_bl(unsigned int *insn_addr, void *func)
|
|
{
|
|
unsigned long funcp = *((unsigned long *)func);
|
|
int offset = funcp - (unsigned long)insn_addr;
|
|
|
|
*insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
|
|
flush_icache_range((unsigned long)insn_addr, 4+
|
|
(unsigned long)insn_addr);
|
|
}
|
|
|
|
static void __init htab_finish_init(void)
|
|
{
|
|
extern unsigned int *htab_call_hpte_insert1;
|
|
extern unsigned int *htab_call_hpte_insert2;
|
|
extern unsigned int *htab_call_hpte_remove;
|
|
extern unsigned int *htab_call_hpte_updatepp;
|
|
|
|
#ifdef CONFIG_PPC_HAS_HASH_64K
|
|
extern unsigned int *ht64_call_hpte_insert1;
|
|
extern unsigned int *ht64_call_hpte_insert2;
|
|
extern unsigned int *ht64_call_hpte_remove;
|
|
extern unsigned int *ht64_call_hpte_updatepp;
|
|
|
|
make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
|
|
make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
|
|
make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
|
|
make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
|
|
#endif /* CONFIG_PPC_HAS_HASH_64K */
|
|
|
|
make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
|
|
make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
|
|
make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
|
|
make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
|
|
}
|
|
|
|
static void __init htab_initialize(void)
|
|
{
|
|
unsigned long table;
|
|
unsigned long pteg_count;
|
|
unsigned long prot;
|
|
unsigned long base = 0, size = 0, limit;
|
|
int i;
|
|
|
|
DBG(" -> htab_initialize()\n");
|
|
|
|
/* Initialize segment sizes */
|
|
htab_init_seg_sizes();
|
|
|
|
/* Initialize page sizes */
|
|
htab_init_page_sizes();
|
|
|
|
if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
|
|
mmu_kernel_ssize = MMU_SEGSIZE_1T;
|
|
mmu_highuser_ssize = MMU_SEGSIZE_1T;
|
|
printk(KERN_INFO "Using 1TB segments\n");
|
|
}
|
|
|
|
/*
|
|
* Calculate the required size of the htab. We want the number of
|
|
* PTEGs to equal one half the number of real pages.
|
|
*/
|
|
htab_size_bytes = htab_get_table_size();
|
|
pteg_count = htab_size_bytes >> 7;
|
|
|
|
htab_hash_mask = pteg_count - 1;
|
|
|
|
if (firmware_has_feature(FW_FEATURE_LPAR)) {
|
|
/* Using a hypervisor which owns the htab */
|
|
htab_address = NULL;
|
|
_SDR1 = 0;
|
|
} else {
|
|
/* Find storage for the HPT. Must be contiguous in
|
|
* the absolute address space. On cell we want it to be
|
|
* in the first 2 Gig so we can use it for IOMMU hacks.
|
|
*/
|
|
if (machine_is(cell))
|
|
limit = 0x80000000;
|
|
else
|
|
limit = 0;
|
|
|
|
table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit);
|
|
|
|
DBG("Hash table allocated at %lx, size: %lx\n", table,
|
|
htab_size_bytes);
|
|
|
|
htab_address = abs_to_virt(table);
|
|
|
|
/* htab absolute addr + encoded htabsize */
|
|
_SDR1 = table + __ilog2(pteg_count) - 11;
|
|
|
|
/* Initialize the HPT with no entries */
|
|
memset((void *)table, 0, htab_size_bytes);
|
|
|
|
/* Set SDR1 */
|
|
mtspr(SPRN_SDR1, _SDR1);
|
|
}
|
|
|
|
prot = pgprot_val(PAGE_KERNEL);
|
|
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
|
|
linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
|
|
1, lmb.rmo_size));
|
|
memset(linear_map_hash_slots, 0, linear_map_hash_count);
|
|
#endif /* CONFIG_DEBUG_PAGEALLOC */
|
|
|
|
/* On U3 based machines, we need to reserve the DART area and
|
|
* _NOT_ map it to avoid cache paradoxes as it's remapped non
|
|
* cacheable later on
|
|
*/
|
|
|
|
/* create bolted the linear mapping in the hash table */
|
|
for (i=0; i < lmb.memory.cnt; i++) {
|
|
base = (unsigned long)__va(lmb.memory.region[i].base);
|
|
size = lmb.memory.region[i].size;
|
|
|
|
DBG("creating mapping for region: %lx..%lx (prot: %x)\n",
|
|
base, size, prot);
|
|
|
|
#ifdef CONFIG_U3_DART
|
|
/* Do not map the DART space. Fortunately, it will be aligned
|
|
* in such a way that it will not cross two lmb regions and
|
|
* will fit within a single 16Mb page.
|
|
* The DART space is assumed to be a full 16Mb region even if
|
|
* we only use 2Mb of that space. We will use more of it later
|
|
* for AGP GART. We have to use a full 16Mb large page.
|
|
*/
|
|
DBG("DART base: %lx\n", dart_tablebase);
|
|
|
|
if (dart_tablebase != 0 && dart_tablebase >= base
|
|
&& dart_tablebase < (base + size)) {
|
|
unsigned long dart_table_end = dart_tablebase + 16 * MB;
|
|
if (base != dart_tablebase)
|
|
BUG_ON(htab_bolt_mapping(base, dart_tablebase,
|
|
__pa(base), prot,
|
|
mmu_linear_psize,
|
|
mmu_kernel_ssize));
|
|
if ((base + size) > dart_table_end)
|
|
BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
|
|
base + size,
|
|
__pa(dart_table_end),
|
|
prot,
|
|
mmu_linear_psize,
|
|
mmu_kernel_ssize));
|
|
continue;
|
|
}
|
|
#endif /* CONFIG_U3_DART */
|
|
BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
|
|
prot, mmu_linear_psize, mmu_kernel_ssize));
|
|
}
|
|
|
|
/*
|
|
* If we have a memory_limit and we've allocated TCEs then we need to
|
|
* explicitly map the TCE area at the top of RAM. We also cope with the
|
|
* case that the TCEs start below memory_limit.
|
|
* tce_alloc_start/end are 16MB aligned so the mapping should work
|
|
* for either 4K or 16MB pages.
|
|
*/
|
|
if (tce_alloc_start) {
|
|
tce_alloc_start = (unsigned long)__va(tce_alloc_start);
|
|
tce_alloc_end = (unsigned long)__va(tce_alloc_end);
|
|
|
|
if (base + size >= tce_alloc_start)
|
|
tce_alloc_start = base + size + 1;
|
|
|
|
BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
|
|
__pa(tce_alloc_start), prot,
|
|
mmu_linear_psize, mmu_kernel_ssize));
|
|
}
|
|
|
|
htab_finish_init();
|
|
|
|
DBG(" <- htab_initialize()\n");
|
|
}
|
|
#undef KB
|
|
#undef MB
|
|
|
|
void __init early_init_mmu(void)
|
|
{
|
|
/* Setup initial STAB address in the PACA */
|
|
get_paca()->stab_real = __pa((u64)&initial_stab);
|
|
get_paca()->stab_addr = (u64)&initial_stab;
|
|
|
|
/* Initialize the MMU Hash table and create the linear mapping
|
|
* of memory. Has to be done before stab/slb initialization as
|
|
* this is currently where the page size encoding is obtained
|
|
*/
|
|
htab_initialize();
|
|
|
|
/* Initialize stab / SLB management except on iSeries
|
|
*/
|
|
if (cpu_has_feature(CPU_FTR_SLB))
|
|
slb_initialize();
|
|
else if (!firmware_has_feature(FW_FEATURE_ISERIES))
|
|
stab_initialize(get_paca()->stab_real);
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
void __cpuinit early_init_mmu_secondary(void)
|
|
{
|
|
/* Initialize hash table for that CPU */
|
|
if (!firmware_has_feature(FW_FEATURE_LPAR))
|
|
mtspr(SPRN_SDR1, _SDR1);
|
|
|
|
/* Initialize STAB/SLB. We use a virtual address as it works
|
|
* in real mode on pSeries and we want a virutal address on
|
|
* iSeries anyway
|
|
*/
|
|
if (cpu_has_feature(CPU_FTR_SLB))
|
|
slb_initialize();
|
|
else
|
|
stab_initialize(get_paca()->stab_addr);
|
|
}
|
|
#endif /* CONFIG_SMP */
|
|
|
|
/*
|
|
* Called by asm hashtable.S for doing lazy icache flush
|
|
*/
|
|
unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
|
|
{
|
|
struct page *page;
|
|
|
|
if (!pfn_valid(pte_pfn(pte)))
|
|
return pp;
|
|
|
|
page = pte_page(pte);
|
|
|
|
/* page is dirty */
|
|
if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
|
|
if (trap == 0x400) {
|
|
flush_dcache_icache_page(page);
|
|
set_bit(PG_arch_1, &page->flags);
|
|
} else
|
|
pp |= HPTE_R_N;
|
|
}
|
|
return pp;
|
|
}
|
|
|
|
#ifdef CONFIG_PPC_MM_SLICES
|
|
unsigned int get_paca_psize(unsigned long addr)
|
|
{
|
|
unsigned long index, slices;
|
|
|
|
if (addr < SLICE_LOW_TOP) {
|
|
slices = get_paca()->context.low_slices_psize;
|
|
index = GET_LOW_SLICE_INDEX(addr);
|
|
} else {
|
|
slices = get_paca()->context.high_slices_psize;
|
|
index = GET_HIGH_SLICE_INDEX(addr);
|
|
}
|
|
return (slices >> (index * 4)) & 0xF;
|
|
}
|
|
|
|
#else
|
|
unsigned int get_paca_psize(unsigned long addr)
|
|
{
|
|
return get_paca()->context.user_psize;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Demote a segment to using 4k pages.
|
|
* For now this makes the whole process use 4k pages.
|
|
*/
|
|
#ifdef CONFIG_PPC_64K_PAGES
|
|
void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
|
|
{
|
|
if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
|
|
return;
|
|
slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
|
|
#ifdef CONFIG_SPU_BASE
|
|
spu_flush_all_slbs(mm);
|
|
#endif
|
|
if (get_paca_psize(addr) != MMU_PAGE_4K) {
|
|
get_paca()->context = mm->context;
|
|
slb_flush_and_rebolt();
|
|
}
|
|
}
|
|
#endif /* CONFIG_PPC_64K_PAGES */
|
|
|
|
#ifdef CONFIG_PPC_SUBPAGE_PROT
|
|
/*
|
|
* This looks up a 2-bit protection code for a 4k subpage of a 64k page.
|
|
* Userspace sets the subpage permissions using the subpage_prot system call.
|
|
*
|
|
* Result is 0: full permissions, _PAGE_RW: read-only,
|
|
* _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
|
|
*/
|
|
static int subpage_protection(pgd_t *pgdir, unsigned long ea)
|
|
{
|
|
struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
|
|
u32 spp = 0;
|
|
u32 **sbpm, *sbpp;
|
|
|
|
if (ea >= spt->maxaddr)
|
|
return 0;
|
|
if (ea < 0x100000000) {
|
|
/* addresses below 4GB use spt->low_prot */
|
|
sbpm = spt->low_prot;
|
|
} else {
|
|
sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
|
|
if (!sbpm)
|
|
return 0;
|
|
}
|
|
sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
|
|
if (!sbpp)
|
|
return 0;
|
|
spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
|
|
|
|
/* extract 2-bit bitfield for this 4k subpage */
|
|
spp >>= 30 - 2 * ((ea >> 12) & 0xf);
|
|
|
|
/* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
|
|
spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
|
|
return spp;
|
|
}
|
|
|
|
#else /* CONFIG_PPC_SUBPAGE_PROT */
|
|
static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/* Result code is:
|
|
* 0 - handled
|
|
* 1 - normal page fault
|
|
* -1 - critical hash insertion error
|
|
* -2 - access not permitted by subpage protection mechanism
|
|
*/
|
|
int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
|
|
{
|
|
void *pgdir;
|
|
unsigned long vsid;
|
|
struct mm_struct *mm;
|
|
pte_t *ptep;
|
|
unsigned hugeshift;
|
|
const struct cpumask *tmp;
|
|
int rc, user_region = 0, local = 0;
|
|
int psize, ssize;
|
|
|
|
DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
|
|
ea, access, trap);
|
|
|
|
if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
|
|
DBG_LOW(" out of pgtable range !\n");
|
|
return 1;
|
|
}
|
|
|
|
/* Get region & vsid */
|
|
switch (REGION_ID(ea)) {
|
|
case USER_REGION_ID:
|
|
user_region = 1;
|
|
mm = current->mm;
|
|
if (! mm) {
|
|
DBG_LOW(" user region with no mm !\n");
|
|
return 1;
|
|
}
|
|
psize = get_slice_psize(mm, ea);
|
|
ssize = user_segment_size(ea);
|
|
vsid = get_vsid(mm->context.id, ea, ssize);
|
|
break;
|
|
case VMALLOC_REGION_ID:
|
|
mm = &init_mm;
|
|
vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
|
|
if (ea < VMALLOC_END)
|
|
psize = mmu_vmalloc_psize;
|
|
else
|
|
psize = mmu_io_psize;
|
|
ssize = mmu_kernel_ssize;
|
|
break;
|
|
default:
|
|
/* Not a valid range
|
|
* Send the problem up to do_page_fault
|
|
*/
|
|
return 1;
|
|
}
|
|
DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
|
|
|
|
/* Get pgdir */
|
|
pgdir = mm->pgd;
|
|
if (pgdir == NULL)
|
|
return 1;
|
|
|
|
/* Check CPU locality */
|
|
tmp = cpumask_of(smp_processor_id());
|
|
if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
|
|
local = 1;
|
|
|
|
#ifndef CONFIG_PPC_64K_PAGES
|
|
/* If we use 4K pages and our psize is not 4K, then we might
|
|
* be hitting a special driver mapping, and need to align the
|
|
* address before we fetch the PTE.
|
|
*
|
|
* It could also be a hugepage mapping, in which case this is
|
|
* not necessary, but it's not harmful, either.
|
|
*/
|
|
if (psize != MMU_PAGE_4K)
|
|
ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
|
|
#endif /* CONFIG_PPC_64K_PAGES */
|
|
|
|
/* Get PTE and page size from page tables */
|
|
ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
|
|
if (ptep == NULL || !pte_present(*ptep)) {
|
|
DBG_LOW(" no PTE !\n");
|
|
return 1;
|
|
}
|
|
|
|
#ifdef CONFIG_HUGETLB_PAGE
|
|
if (hugeshift)
|
|
return __hash_page_huge(ea, access, vsid, ptep, trap, local,
|
|
ssize, hugeshift, psize);
|
|
#endif /* CONFIG_HUGETLB_PAGE */
|
|
|
|
#ifndef CONFIG_PPC_64K_PAGES
|
|
DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
|
|
#else
|
|
DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
|
|
pte_val(*(ptep + PTRS_PER_PTE)));
|
|
#endif
|
|
/* Pre-check access permissions (will be re-checked atomically
|
|
* in __hash_page_XX but this pre-check is a fast path
|
|
*/
|
|
if (access & ~pte_val(*ptep)) {
|
|
DBG_LOW(" no access !\n");
|
|
return 1;
|
|
}
|
|
|
|
/* Do actual hashing */
|
|
#ifdef CONFIG_PPC_64K_PAGES
|
|
/* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
|
|
if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
|
|
demote_segment_4k(mm, ea);
|
|
psize = MMU_PAGE_4K;
|
|
}
|
|
|
|
/* If this PTE is non-cacheable and we have restrictions on
|
|
* using non cacheable large pages, then we switch to 4k
|
|
*/
|
|
if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
|
|
(pte_val(*ptep) & _PAGE_NO_CACHE)) {
|
|
if (user_region) {
|
|
demote_segment_4k(mm, ea);
|
|
psize = MMU_PAGE_4K;
|
|
} else if (ea < VMALLOC_END) {
|
|
/*
|
|
* some driver did a non-cacheable mapping
|
|
* in vmalloc space, so switch vmalloc
|
|
* to 4k pages
|
|
*/
|
|
printk(KERN_ALERT "Reducing vmalloc segment "
|
|
"to 4kB pages because of "
|
|
"non-cacheable mapping\n");
|
|
psize = mmu_vmalloc_psize = MMU_PAGE_4K;
|
|
#ifdef CONFIG_SPU_BASE
|
|
spu_flush_all_slbs(mm);
|
|
#endif
|
|
}
|
|
}
|
|
if (user_region) {
|
|
if (psize != get_paca_psize(ea)) {
|
|
get_paca()->context = mm->context;
|
|
slb_flush_and_rebolt();
|
|
}
|
|
} else if (get_paca()->vmalloc_sllp !=
|
|
mmu_psize_defs[mmu_vmalloc_psize].sllp) {
|
|
get_paca()->vmalloc_sllp =
|
|
mmu_psize_defs[mmu_vmalloc_psize].sllp;
|
|
slb_vmalloc_update();
|
|
}
|
|
#endif /* CONFIG_PPC_64K_PAGES */
|
|
|
|
#ifdef CONFIG_PPC_HAS_HASH_64K
|
|
if (psize == MMU_PAGE_64K)
|
|
rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
|
|
else
|
|
#endif /* CONFIG_PPC_HAS_HASH_64K */
|
|
{
|
|
int spp = subpage_protection(pgdir, ea);
|
|
if (access & spp)
|
|
rc = -2;
|
|
else
|
|
rc = __hash_page_4K(ea, access, vsid, ptep, trap,
|
|
local, ssize, spp);
|
|
}
|
|
|
|
#ifndef CONFIG_PPC_64K_PAGES
|
|
DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
|
|
#else
|
|
DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
|
|
pte_val(*(ptep + PTRS_PER_PTE)));
|
|
#endif
|
|
DBG_LOW(" -> rc=%d\n", rc);
|
|
return rc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hash_page);
|
|
|
|
void hash_preload(struct mm_struct *mm, unsigned long ea,
|
|
unsigned long access, unsigned long trap)
|
|
{
|
|
unsigned long vsid;
|
|
void *pgdir;
|
|
pte_t *ptep;
|
|
unsigned long flags;
|
|
int local = 0;
|
|
int ssize;
|
|
|
|
BUG_ON(REGION_ID(ea) != USER_REGION_ID);
|
|
|
|
#ifdef CONFIG_PPC_MM_SLICES
|
|
/* We only prefault standard pages for now */
|
|
if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
|
|
return;
|
|
#endif
|
|
|
|
DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
|
|
" trap=%lx\n", mm, mm->pgd, ea, access, trap);
|
|
|
|
/* Get Linux PTE if available */
|
|
pgdir = mm->pgd;
|
|
if (pgdir == NULL)
|
|
return;
|
|
ptep = find_linux_pte(pgdir, ea);
|
|
if (!ptep)
|
|
return;
|
|
|
|
#ifdef CONFIG_PPC_64K_PAGES
|
|
/* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
|
|
* a 64K kernel), then we don't preload, hash_page() will take
|
|
* care of it once we actually try to access the page.
|
|
* That way we don't have to duplicate all of the logic for segment
|
|
* page size demotion here
|
|
*/
|
|
if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
|
|
return;
|
|
#endif /* CONFIG_PPC_64K_PAGES */
|
|
|
|
/* Get VSID */
|
|
ssize = user_segment_size(ea);
|
|
vsid = get_vsid(mm->context.id, ea, ssize);
|
|
|
|
/* Hash doesn't like irqs */
|
|
local_irq_save(flags);
|
|
|
|
/* Is that local to this CPU ? */
|
|
if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
|
|
local = 1;
|
|
|
|
/* Hash it in */
|
|
#ifdef CONFIG_PPC_HAS_HASH_64K
|
|
if (mm->context.user_psize == MMU_PAGE_64K)
|
|
__hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
|
|
else
|
|
#endif /* CONFIG_PPC_HAS_HASH_64K */
|
|
__hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
|
|
subpage_protection(pgdir, ea));
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/* WARNING: This is called from hash_low_64.S, if you change this prototype,
|
|
* do not forget to update the assembly call site !
|
|
*/
|
|
void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
|
|
int local)
|
|
{
|
|
unsigned long hash, index, shift, hidx, slot;
|
|
|
|
DBG_LOW("flush_hash_page(va=%016x)\n", va);
|
|
pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
|
|
hash = hpt_hash(va, shift, ssize);
|
|
hidx = __rpte_to_hidx(pte, index);
|
|
if (hidx & _PTEIDX_SECONDARY)
|
|
hash = ~hash;
|
|
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
|
|
slot += hidx & _PTEIDX_GROUP_IX;
|
|
DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
|
|
ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
|
|
} pte_iterate_hashed_end();
|
|
}
|
|
|
|
void flush_hash_range(unsigned long number, int local)
|
|
{
|
|
if (ppc_md.flush_hash_range)
|
|
ppc_md.flush_hash_range(number, local);
|
|
else {
|
|
int i;
|
|
struct ppc64_tlb_batch *batch =
|
|
&__get_cpu_var(ppc64_tlb_batch);
|
|
|
|
for (i = 0; i < number; i++)
|
|
flush_hash_page(batch->vaddr[i], batch->pte[i],
|
|
batch->psize, batch->ssize, local);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* low_hash_fault is called when we the low level hash code failed
|
|
* to instert a PTE due to an hypervisor error
|
|
*/
|
|
void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
|
|
{
|
|
if (user_mode(regs)) {
|
|
#ifdef CONFIG_PPC_SUBPAGE_PROT
|
|
if (rc == -2)
|
|
_exception(SIGSEGV, regs, SEGV_ACCERR, address);
|
|
else
|
|
#endif
|
|
_exception(SIGBUS, regs, BUS_ADRERR, address);
|
|
} else
|
|
bad_page_fault(regs, address, SIGBUS);
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
|
|
{
|
|
unsigned long hash, hpteg;
|
|
unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
|
|
unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
|
|
unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
|
|
int ret;
|
|
|
|
hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
|
|
hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
|
|
|
|
ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
|
|
mode, HPTE_V_BOLTED,
|
|
mmu_linear_psize, mmu_kernel_ssize);
|
|
BUG_ON (ret < 0);
|
|
spin_lock(&linear_map_hash_lock);
|
|
BUG_ON(linear_map_hash_slots[lmi] & 0x80);
|
|
linear_map_hash_slots[lmi] = ret | 0x80;
|
|
spin_unlock(&linear_map_hash_lock);
|
|
}
|
|
|
|
static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
|
|
{
|
|
unsigned long hash, hidx, slot;
|
|
unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
|
|
unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
|
|
|
|
hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
|
|
spin_lock(&linear_map_hash_lock);
|
|
BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
|
|
hidx = linear_map_hash_slots[lmi] & 0x7f;
|
|
linear_map_hash_slots[lmi] = 0;
|
|
spin_unlock(&linear_map_hash_lock);
|
|
if (hidx & _PTEIDX_SECONDARY)
|
|
hash = ~hash;
|
|
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
|
|
slot += hidx & _PTEIDX_GROUP_IX;
|
|
ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
|
|
}
|
|
|
|
void kernel_map_pages(struct page *page, int numpages, int enable)
|
|
{
|
|
unsigned long flags, vaddr, lmi;
|
|
int i;
|
|
|
|
local_irq_save(flags);
|
|
for (i = 0; i < numpages; i++, page++) {
|
|
vaddr = (unsigned long)page_address(page);
|
|
lmi = __pa(vaddr) >> PAGE_SHIFT;
|
|
if (lmi >= linear_map_hash_count)
|
|
continue;
|
|
if (enable)
|
|
kernel_map_linear_page(vaddr, lmi);
|
|
else
|
|
kernel_unmap_linear_page(vaddr, lmi);
|
|
}
|
|
local_irq_restore(flags);
|
|
}
|
|
#endif /* CONFIG_DEBUG_PAGEALLOC */
|