07d9714365
Minimal definition of register set for 378x boards Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
80 lines
3.5 KiB
C
80 lines
3.5 KiB
C
/*
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* STMP APBX Register Definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ARCH_ARM___APBX_H
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#define __ARCH_ARM___APBX_H 1
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#include <mach/stmp3xxx_regs.h>
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#define REGS_APBX_BASE (REGS_BASE + 0x24000)
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#define REGS_APBX_BASE_PHYS (0x80024000)
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#define REGS_APBX_SIZE 0x00002000
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HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00000000)
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#define HW_APBX_CTRL0_ADDR (REGS_APBX_BASE + 0x00000000)
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#define BM_APBX_CTRL0_SFTRST 0x80000000
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#define BM_APBX_CTRL0_CLKGATE 0x40000000
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HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x00000010)
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HW_REGISTER(HW_APBX_CTRL2, REGS_APBX_BASE, 0x00000020)
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HW_REGISTER(HW_APBX_CHANNEL_CTRL, REGS_APBX_BASE, 0x00000030)
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#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16
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#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000
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#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v) \
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(((v) << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL) & \
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BM_APBX_CHANNEL_CTRL_RESET_CHANNEL)
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HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x00000040)
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HW_REGISTER_0_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x00000100, 0x70)
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HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x00000110, 0x70)
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HW_REGISTER_0_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x00000120, 0x70)
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#define BP_APBX_CHn_CMD_XFER_COUNT 16
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#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
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#define BF_APBX_CHn_CMD_XFER_COUNT(v) \
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(((v) << 16) & BM_APBX_CHn_CMD_XFER_COUNT)
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#define BP_APBX_CHn_CMD_CMDWORDS 12
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#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
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#define BF_APBX_CHn_CMD_CMDWORDS(v) \
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(((v) << 12) & BM_APBX_CHn_CMD_CMDWORDS)
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#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100
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#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
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#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
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#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
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#define BM_APBX_CHn_CMD_CHAIN 0x00000004
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#define BP_APBX_CHn_CMD_COMMAND 0
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#define BM_APBX_CHn_CMD_COMMAND 0x00000003
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#define BF_APBX_CHn_CMD_COMMAND(v) \
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(((v) << 0) & BM_APBX_CHn_CMD_COMMAND)
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#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
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#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1
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#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2
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HW_REGISTER_0_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x00000130, 0x70)
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HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x00000140, 0x70)
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#define BP_APBX_CHn_SEMA_PHORE 16
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#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
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#define BF_APBX_CHn_SEMA_PHORE(v) \
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(((v) << 16) & BM_APBX_CHn_SEMA_PHORE)
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#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
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#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
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#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \
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(((v) << 0) & BM_APBX_CHn_SEMA_INCREMENT_SEMA)
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HW_REGISTER_0_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x00000150, 0x70)
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HW_REGISTER_0_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0x00000160, 0x70)
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HW_REGISTER_0(HW_APBX_VERSION, REGS_APBX_BASE, 0x00000800)
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#endif /* __ARCH_ARM___APBX_H */
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