5f19f14fed
At present reserving the IRLs in the IRQ bitmap in addition to the dropping of the legacy IRQ pre-allocation prevent IRL IRQs from being allocated for the x3proto board. The only reason to permit reservations was to lock down possible hardware vectors prior to dynamic IRQ scanning, but this doesn't matter much given that the hardware controller configuration is sorted before we get around to doing any dynamic IRQ allocation anyways. Beyond that, all of the tables are __init annotated, so quite a bit more work would need to be done to support reconfiguring things like IRL controllers on the fly, much more than would ever make it worth the hassle. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
150 lines
3.4 KiB
C
150 lines
3.4 KiB
C
#ifndef __SH_INTC_H
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#define __SH_INTC_H
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#include <linux/ioport.h>
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#ifdef CONFIG_SUPERH
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#define INTC_NR_IRQS 512
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#else
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#define INTC_NR_IRQS 1024
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#endif
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/*
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* Convert back and forth between INTEVT and IRQ values.
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*/
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#ifdef CONFIG_CPU_HAS_INTEVT
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#define evt2irq(evt) (((evt) >> 5) - 16)
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#define irq2evt(irq) (((irq) + 16) << 5)
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#else
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#define evt2irq(evt) (evt)
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#define irq2evt(irq) (irq)
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#endif
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typedef unsigned char intc_enum;
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struct intc_vect {
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intc_enum enum_id;
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unsigned short vect;
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};
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#define INTC_VECT(enum_id, vect) { enum_id, vect }
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#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
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struct intc_group {
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intc_enum enum_id;
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intc_enum enum_ids[32];
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};
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#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
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struct intc_subgroup {
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unsigned long reg, reg_width;
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intc_enum parent_id;
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intc_enum enum_ids[32];
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};
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struct intc_mask_reg {
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unsigned long set_reg, clr_reg, reg_width;
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intc_enum enum_ids[32];
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#ifdef CONFIG_INTC_BALANCING
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unsigned long dist_reg;
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#endif
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#ifdef CONFIG_SMP
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unsigned long smp;
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#endif
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};
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struct intc_prio_reg {
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unsigned long set_reg, clr_reg, reg_width, field_width;
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intc_enum enum_ids[16];
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#ifdef CONFIG_SMP
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unsigned long smp;
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#endif
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};
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struct intc_sense_reg {
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unsigned long reg, reg_width, field_width;
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intc_enum enum_ids[16];
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};
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#ifdef CONFIG_INTC_BALANCING
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#define INTC_SMP_BALANCING(reg) .dist_reg = (reg)
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#else
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#define INTC_SMP_BALANCING(reg)
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#endif
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#ifdef CONFIG_SMP
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#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
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#else
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#define INTC_SMP(stride, nr)
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#endif
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struct intc_hw_desc {
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struct intc_vect *vectors;
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unsigned int nr_vectors;
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struct intc_group *groups;
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unsigned int nr_groups;
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struct intc_mask_reg *mask_regs;
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unsigned int nr_mask_regs;
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struct intc_prio_reg *prio_regs;
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unsigned int nr_prio_regs;
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struct intc_sense_reg *sense_regs;
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unsigned int nr_sense_regs;
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struct intc_mask_reg *ack_regs;
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unsigned int nr_ack_regs;
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struct intc_subgroup *subgroups;
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unsigned int nr_subgroups;
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};
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#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a)
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#define INTC_HW_DESC(vectors, groups, mask_regs, \
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prio_regs, sense_regs, ack_regs) \
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{ \
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_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
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_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
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_INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs), \
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}
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struct intc_desc {
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char *name;
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struct resource *resource;
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unsigned int num_resources;
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intc_enum force_enable;
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intc_enum force_disable;
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bool skip_syscore_suspend;
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struct intc_hw_desc hw;
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};
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#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
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mask_regs, prio_regs, sense_regs) \
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struct intc_desc symbol __initdata = { \
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.name = chipname, \
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.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
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prio_regs, sense_regs, NULL), \
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}
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#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
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mask_regs, prio_regs, sense_regs, ack_regs) \
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struct intc_desc symbol __initdata = { \
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.name = chipname, \
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.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
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prio_regs, sense_regs, ack_regs), \
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}
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int register_intc_controller(struct intc_desc *desc);
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int intc_set_priority(unsigned int irq, unsigned int prio);
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int intc_irq_lookup(const char *chipname, intc_enum enum_id);
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void intc_finalize(void);
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#ifdef CONFIG_INTC_USERIMASK
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int register_intc_userimask(unsigned long addr);
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#else
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static inline int register_intc_userimask(unsigned long addr)
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{
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return 0;
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}
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#endif
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#endif /* __SH_INTC_H */
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