fcba914542
This is the third and smallest of the SoC specific updates.
Changes include:
* SMP support for the Xilinx zynq platform
* Smaller imx changes
* LPAE support for mvebu
* Moving the orion5x, kirkwood, dove and mvebu platforms
to a common "mbus" driver for their internal devices.
It would be good to get feedback on the location of the "mbus"
driver. Since this is used on multiple platforms may potentially
get shared with other architectures (powerpc and arm64), it
was moved to drivers/bus/. We expect other similar drivers to
get moved to the same place in order to avoid creating more
top-level directories under drivers/ or cluttering up the
messy drivers/misc/ even more.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAUYgifmCrR//JCVInAQLZ6A//VD38ocUx9RPC8rOgrkzQxcMTh3wFghoA
BVvS8fcAmhZYA5+GpTYBm+5XH2Jvu6Pv0hrba8TOeEhyZJxiWA6vg0cWWmnvZLDC
Q0uubhqIhv32I2Oq4uJb/VyzcCrQFrnjhw9HHphy7YlGKKBUFWrbgTaOypwbgXr9
DnB7u04DvaKcUjZb4Y0HaUDM7qWMFDPbKKF5WMZPqjocnjsiBQ2JMw+2KByliWR3
mCI+FdickpDYSVp9V9iRM6F73cItknjZIzQs1RYg/GSuPSWkWTdfzE1Blk/561Fo
QDrNDhnXHlt+bmQRKGWel2gDWBZW47Wj+XkjGpWDFh+e/l3vNJq0hrzXizuRCLSw
/2VefXyd3jNj8UWL3+GCA4dnw8fx14dgfNJ2iu7kg6l4ggwpJ05ToxabkLFlTRwy
LloDFjswiTBi75YdQRQCV/95NIxvIQIkbytPrk5zQWVwg8ZXoicgzRRUL5gifLh+
WE+zaY/A5e1fXN/XS70hvbp2ROZtfGOdunUR9XFR8KNqDoJDlqtrlV3Pjh75YY8G
JUmCKQjzfubr5WHskPBGCtsSb1455MEIFVANEtlJyOEKp6ytXfpVvrrZtAvmD6Ep
07dOqOgflnuZPk7H0JOf7mTf9L+fmNp4ubjRqcs9ZfPsEGoQFqBtpLF6JQbxUYGd
j69lW3jEM3o=
=rQsu
-----END PGP SIGNATURE-----
Merge tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates (part 3) from Arnd Bergmann:
"This is the third and smallest of the SoC specific updates. Changes
include:
- SMP support for the Xilinx zynq platform
- Smaller imx changes
- LPAE support for mvebu
- Moving the orion5x, kirkwood, dove and mvebu platforms to a common
"mbus" driver for their internal devices.
It would be good to get feedback on the location of the "mbus" driver.
Since this is used on multiple platforms may potentially get shared
with other architectures (powerpc and arm64), it was moved to
drivers/bus/. We expect other similar drivers to get moved to the
same place in order to avoid creating more top-level directories under
drivers/ or cluttering up the messy drivers/misc/ even more."
* tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits)
ARM: imx: reset_controller may be disabled
ARM: mvebu: Align the internal registers virtual base to support LPAE
ARM: mvebu: Limit the DMA zone when LPAE is selected
arm: plat-orion: remove addr-map code
arm: mach-mv78xx0: convert to use the mvebu-mbus driver
arm: mach-orion5x: convert to use mvebu-mbus driver
arm: mach-dove: convert to use mvebu-mbus driver
arm: mach-kirkwood: convert to use mvebu-mbus driver
arm: mach-mvebu: convert to use mvebu-mbus driver
ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock
ARM i.MX53: tve_di clock is not part of the CCM, but of TVE
ARM i.MX53: make tve_ext_sel propagate rate change to PLL
ARM i.MX53: Remove unused tve_gate clkdev entry
ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree
ARM: i.MX5: Add PATA and SRTC clocks
ARM: imx: do not bring up unavailable cores
ARM: imx: add initial imx6dl support
ARM: imx1: mm: add call to mxc_device_init
ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS
ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS
...
141 lines
3.1 KiB
C
141 lines
3.1 KiB
C
/*
|
|
* Copyright 2011-2013 Freescale Semiconductor, Inc.
|
|
* Copyright 2011 Linaro Ltd.
|
|
*
|
|
* The code contained herein is licensed under the GNU General Public
|
|
* License. You may obtain a copy of the GNU General Public License
|
|
* Version 2 or later at the following locations:
|
|
*
|
|
* http://www.opensource.org/licenses/gpl-license.html
|
|
* http://www.gnu.org/copyleft/gpl.html
|
|
*/
|
|
|
|
#include <linux/io.h>
|
|
#include <linux/irq.h>
|
|
#include <linux/of.h>
|
|
#include <linux/of_address.h>
|
|
#include <linux/of_irq.h>
|
|
#include <linux/irqchip/arm-gic.h>
|
|
#include "common.h"
|
|
|
|
#define GPC_IMR1 0x008
|
|
#define GPC_PGC_CPU_PDN 0x2a0
|
|
|
|
#define IMR_NUM 4
|
|
|
|
static void __iomem *gpc_base;
|
|
static u32 gpc_wake_irqs[IMR_NUM];
|
|
static u32 gpc_saved_imrs[IMR_NUM];
|
|
|
|
void imx_gpc_pre_suspend(void)
|
|
{
|
|
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
|
|
int i;
|
|
|
|
/* Tell GPC to power off ARM core when suspend */
|
|
writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
|
|
|
|
for (i = 0; i < IMR_NUM; i++) {
|
|
gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
|
|
writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
|
|
}
|
|
}
|
|
|
|
void imx_gpc_post_resume(void)
|
|
{
|
|
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
|
|
int i;
|
|
|
|
/* Keep ARM core powered on for other low-power modes */
|
|
writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
|
|
|
|
for (i = 0; i < IMR_NUM; i++)
|
|
writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
|
|
}
|
|
|
|
static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
|
|
{
|
|
unsigned int idx = d->irq / 32 - 1;
|
|
u32 mask;
|
|
|
|
/* Sanity check for SPI irq */
|
|
if (d->irq < 32)
|
|
return -EINVAL;
|
|
|
|
mask = 1 << d->irq % 32;
|
|
gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
|
|
gpc_wake_irqs[idx] & ~mask;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void imx_gpc_mask_all(void)
|
|
{
|
|
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
|
|
int i;
|
|
|
|
for (i = 0; i < IMR_NUM; i++) {
|
|
gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
|
|
writel_relaxed(~0, reg_imr1 + i * 4);
|
|
}
|
|
|
|
}
|
|
|
|
void imx_gpc_restore_all(void)
|
|
{
|
|
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
|
|
int i;
|
|
|
|
for (i = 0; i < IMR_NUM; i++)
|
|
writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
|
|
}
|
|
|
|
static void imx_gpc_irq_unmask(struct irq_data *d)
|
|
{
|
|
void __iomem *reg;
|
|
u32 val;
|
|
|
|
/* Sanity check for SPI irq */
|
|
if (d->irq < 32)
|
|
return;
|
|
|
|
reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
|
|
val = readl_relaxed(reg);
|
|
val &= ~(1 << d->irq % 32);
|
|
writel_relaxed(val, reg);
|
|
}
|
|
|
|
static void imx_gpc_irq_mask(struct irq_data *d)
|
|
{
|
|
void __iomem *reg;
|
|
u32 val;
|
|
|
|
/* Sanity check for SPI irq */
|
|
if (d->irq < 32)
|
|
return;
|
|
|
|
reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4;
|
|
val = readl_relaxed(reg);
|
|
val |= 1 << (d->irq % 32);
|
|
writel_relaxed(val, reg);
|
|
}
|
|
|
|
void __init imx_gpc_init(void)
|
|
{
|
|
struct device_node *np;
|
|
int i;
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
|
|
gpc_base = of_iomap(np, 0);
|
|
WARN_ON(!gpc_base);
|
|
|
|
/* Initially mask all interrupts */
|
|
for (i = 0; i < IMR_NUM; i++)
|
|
writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
|
|
|
|
/* Register GPC as the secondary interrupt controller behind GIC */
|
|
gic_arch_extn.irq_mask = imx_gpc_irq_mask;
|
|
gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
|
|
gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
|
|
}
|