0cd61b68c3
Untested, but this should fix up the bulk of the totally mechanical issues, and should make the actual detail fixing easier. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
111 lines
2.5 KiB
C
111 lines
2.5 KiB
C
/*
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* linux/arch/arm/mach-shark/irq.c
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*
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* by Alexander Schulz
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*
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* derived from linux/arch/ppc/kernel/i8259.c and:
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* include/asm-arm/arch-ebsa110/irq.h
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* Copyright (C) 1996-1998 Russell King
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*/
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#include <linux/init.h>
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#include <linux/fs.h>
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#include <linux/ptrace.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/mach/irq.h>
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/*
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* 8259A PIC functions to handle ISA devices:
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*/
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/*
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* This contains the irq mask for both 8259A irq controllers,
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* Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb)
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*/
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static unsigned char cached_irq_mask[2] = { 0xfb, 0xff };
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/*
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* These have to be protected by the irq controller spinlock
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* before being called.
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*/
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static void shark_disable_8259A_irq(unsigned int irq)
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{
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unsigned int mask;
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if (irq<8) {
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mask = 1 << irq;
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cached_irq_mask[0] |= mask;
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outb(cached_irq_mask[1],0xA1);
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} else {
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mask = 1 << (irq-8);
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cached_irq_mask[1] |= mask;
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outb(cached_irq_mask[0],0x21);
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}
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}
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static void shark_enable_8259A_irq(unsigned int irq)
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{
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unsigned int mask;
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if (irq<8) {
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mask = ~(1 << irq);
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cached_irq_mask[0] &= mask;
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outb(cached_irq_mask[0],0x21);
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} else {
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mask = ~(1 << (irq-8));
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cached_irq_mask[1] &= mask;
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outb(cached_irq_mask[1],0xA1);
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}
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}
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static void shark_ack_8259A_irq(unsigned int irq){}
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static irqreturn_t bogus_int(int irq, void *dev_id)
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{
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printk("Got interrupt %i!\n",irq);
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return IRQ_NONE;
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}
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static struct irqaction cascade;
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static struct irq_chip fb_chip = {
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.name = "XT-PIC",
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.ack = shark_ack_8259A_irq,
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.mask = shark_disable_8259A_irq,
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.unmask = shark_enable_8259A_irq,
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};
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void __init shark_init_irq(void)
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{
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int irq;
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for (irq = 0; irq < NR_IRQS; irq++) {
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set_irq_chip(irq, &fb_chip);
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set_irq_handler(irq, do_edge_IRQ);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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/* init master interrupt controller */
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outb(0x11, 0x20); /* Start init sequence, edge triggered (level: 0x19)*/
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outb(0x00, 0x21); /* Vector base */
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outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */
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outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/
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outb(0x0A, 0x20);
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/* init slave interrupt controller */
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outb(0x11, 0xA0); /* Start init sequence, edge triggered */
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outb(0x08, 0xA1); /* Vector base */
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outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */
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outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */
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outb(0x0A, 0xA0);
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outb(cached_irq_mask[1],0xA1);
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outb(cached_irq_mask[0],0x21);
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//request_region(0x20,0x2,"pic1");
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//request_region(0xA0,0x2,"pic2");
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cascade.handler = bogus_int;
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cascade.name = "cascade";
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setup_irq(2,&cascade);
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}
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