15700039b1
We don't need it, we have a perfectly good set of debug tools. For this pass keep a few debug printks around which are "should not happen" items Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
456 lines
13 KiB
C
456 lines
13 KiB
C
/*
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* Agere Systems Inc.
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* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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* http://www.agere.com
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*
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*------------------------------------------------------------------------------
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*
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* et1310_eeprom.c - Code used to access the device's EEPROM
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*
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*------------------------------------------------------------------------------
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*
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* SOFTWARE LICENSE
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*
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* This software is provided subject to the following terms and conditions,
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* which you should read carefully before using the software. Using this
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* software indicates your acceptance of these terms and conditions. If you do
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* not agree with these terms and conditions, do not use the software.
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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*
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* Redistribution and use in source or binary forms, with or without
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* modifications, are permitted provided that the following conditions are met:
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*
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* . Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following Disclaimer as comments in the code as
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* well as in the documentation and/or other materials provided with the
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* distribution.
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*
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* . Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following Disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* . Neither the name of Agere Systems Inc. nor the names of the contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* Disclaimer
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
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* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*
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*/
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#include "et131x_version.h"
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#include "et131x_defs.h"
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/slab.h>
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#include <linux/ctype.h>
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#include <linux/string.h>
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#include <linux/timer.h>
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#include <linux/interrupt.h>
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#include <linux/in.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <asm/system.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/if_arp.h>
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#include <linux/ioport.h>
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#include "et1310_phy.h"
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#include "et1310_pm.h"
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#include "et1310_jagcore.h"
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#include "et1310_eeprom.h"
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#include "et131x_adapter.h"
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#include "et131x_initpci.h"
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#include "et131x_isr.h"
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#include "et1310_tx.h"
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/*
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* EEPROM Defines
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*/
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/* LBCIF Register Groups (addressed via 32-bit offsets) */
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#define LBCIF_DWORD0_GROUP_OFFSET 0xAC
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#define LBCIF_DWORD1_GROUP_OFFSET 0xB0
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/* LBCIF Registers (addressed via 8-bit offsets) */
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#define LBCIF_ADDRESS_REGISTER_OFFSET 0xAC
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#define LBCIF_DATA_REGISTER_OFFSET 0xB0
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#define LBCIF_CONTROL_REGISTER_OFFSET 0xB1
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#define LBCIF_STATUS_REGISTER_OFFSET 0xB2
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/* LBCIF Control Register Bits */
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#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
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#define LBCIF_CONTROL_PAGE_WRITE 0x02
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#define LBCIF_CONTROL_UNUSED1 0x04
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#define LBCIF_CONTROL_EEPROM_RELOAD 0x08
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#define LBCIF_CONTROL_UNUSED2 0x10
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#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
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#define LBCIF_CONTROL_I2C_WRITE 0x40
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#define LBCIF_CONTROL_LBCIF_ENABLE 0x80
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/* LBCIF Status Register Bits */
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#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
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#define LBCIF_STATUS_I2C_IDLE 0x02
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#define LBCIF_STATUS_ACK_ERROR 0x04
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#define LBCIF_STATUS_GENERAL_ERROR 0x08
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#define LBCIF_STATUS_UNUSED 0x30
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#define LBCIF_STATUS_CHECKSUM_ERROR 0x40
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#define LBCIF_STATUS_EEPROM_PRESENT 0x80
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/* Miscellaneous Constraints */
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#define MAX_NUM_REGISTER_POLLS 1000
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#define MAX_NUM_WRITE_RETRIES 2
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/*
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* Define macros that allow individual register values to be extracted from a
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* DWORD1 register grouping
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*/
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#define EXTRACT_DATA_REGISTER(x) (u8)(x & 0xFF)
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#define EXTRACT_STATUS_REGISTER(x) (u8)((x >> 16) & 0xFF)
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#define EXTRACT_CONTROL_REG(x) (u8)((x >> 8) & 0xFF)
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/**
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* EepromWriteByte - Write a byte to the ET1310's EEPROM
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* @etdev: pointer to our private adapter structure
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* @addr: the address to write
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* @data: the value to write
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*
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* Returns SUCCESS or FAILURE
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*/
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int EepromWriteByte(struct et131x_adapter *etdev, u32 addr, u8 data)
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{
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struct pci_dev *pdev = etdev->pdev;
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int index;
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int retries;
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int err = 0;
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int i2c_wack = 0;
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int writeok = 0;
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u8 control;
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u8 status = 0;
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u32 dword1 = 0;
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u32 val = 0;
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/*
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* The following excerpt is from "Serial EEPROM HW Design
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* Specification" Version 0.92 (9/20/2004):
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*
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* Single Byte Writes
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*
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* For an EEPROM, an I2C single byte write is defined as a START
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* condition followed by the device address, EEPROM address, one byte
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* of data and a STOP condition. The STOP condition will trigger the
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* EEPROM's internally timed write cycle to the nonvolatile memory.
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* All inputs are disabled during this write cycle and the EEPROM will
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* not respond to any access until the internal write is complete.
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* The steps to execute a single byte write are as follows:
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*
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* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
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* bits 7,1:0 both equal to 1, at least once after reset.
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* Subsequent operations need only to check that bits 1:0 are
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* equal to 1 prior to starting a single byte write.
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*
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* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
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* and bits 1:0 both =0. Bit 5 should be set according to the
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* type of EEPROM being accessed (1=two byte addressing, 0=one
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* byte addressing).
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*
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* 3. Write the address to the LBCIF Address Register.
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*
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* 4. Write the data to the LBCIF Data Register (the I2C write will
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* begin).
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*
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* 5. Monitor bit 1:0 of the LBCIF Status Register. When bits 1:0 are
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* both equal to 1, the I2C write has completed and the internal
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* write cycle of the EEPROM is about to start. (bits 1:0 = 01 is
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* a legal state while waiting from both equal to 1, but bits
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* 1:0 = 10 is invalid and implies that something is broken).
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*
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* 6. Check bit 3 of the LBCIF Status Register. If equal to 1, an
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* error has occurred.
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*
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* 7. Check bit 2 of the LBCIF Status Register. If equal to 1 an ACK
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* error has occurred on the address phase of the write. This
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* could be due to an actual hardware failure or the EEPROM may
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* still be in its internal write cycle from a previous write.
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* This write operation was ignored and must be repeated later.
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*
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* 8. Set bit 6 of the LBCIF Control Register = 0. If another write is
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* required, go to step 1.
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*/
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/* Step 1: */
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for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {
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/* Read registers grouped in DWORD1 */
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if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
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&dword1)) {
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err = 1;
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break;
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}
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status = EXTRACT_STATUS_REGISTER(dword1);
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if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
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status & LBCIF_STATUS_I2C_IDLE)
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/* bits 1:0 are equal to 1 */
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break;
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}
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if (err || (index >= MAX_NUM_REGISTER_POLLS))
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return FAILURE;
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/* Step 2: */
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control = 0;
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control |= LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE;
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if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
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control)) {
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return FAILURE;
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}
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i2c_wack = 1;
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/* Prepare EEPROM address for Step 3 */
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for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
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/* Step 3:*/
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if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,
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addr)) {
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break;
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}
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/* Step 4: */
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if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER_OFFSET,
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data)) {
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break;
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}
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/* Step 5: */
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for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {
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/* Read registers grouped in DWORD1 */
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if (pci_read_config_dword(pdev,
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LBCIF_DWORD1_GROUP_OFFSET,
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&dword1)) {
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err = 1;
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break;
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}
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status = EXTRACT_STATUS_REGISTER(dword1);
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if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
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status & LBCIF_STATUS_I2C_IDLE) {
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/* I2C write complete */
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break;
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}
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}
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if (err || (index >= MAX_NUM_REGISTER_POLLS))
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break;
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/*
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* Step 6: Don't break here if we are revision 1, this is
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* so we do a blind write for load bug.
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*/
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if (status & LBCIF_STATUS_GENERAL_ERROR
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&& etdev->pdev->revision == 0) {
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break;
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}
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/* Step 7 */
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if (status & LBCIF_STATUS_ACK_ERROR) {
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/*
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* This could be due to an actual hardware failure
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* or the EEPROM may still be in its internal write
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* cycle from a previous write. This write operation
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* was ignored and must be repeated later.
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*/
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udelay(10);
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continue;
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}
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writeok = 1;
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break;
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}
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/* Step 8: */
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udelay(10);
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index = 0;
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while (i2c_wack) {
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control &= ~LBCIF_CONTROL_I2C_WRITE;
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if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
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control)) {
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writeok = 0;
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}
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/* Do read until internal ACK_ERROR goes away meaning write
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* completed
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*/
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do {
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pci_write_config_dword(pdev,
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LBCIF_ADDRESS_REGISTER_OFFSET,
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addr);
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do {
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pci_read_config_dword(pdev,
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LBCIF_DATA_REGISTER_OFFSET, &val);
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} while ((val & 0x00010000) == 0);
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} while (val & 0x00040000);
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control = EXTRACT_CONTROL_REG(val);
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if (control != 0xC0 || index == 10000)
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break;
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index++;
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}
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return writeok ? SUCCESS : FAILURE;
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}
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/**
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* EepromReadByte - Read a byte from the ET1310's EEPROM
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* @etdev: pointer to our private adapter structure
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* @addr: the address from which to read
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* @pdata: a pointer to a byte in which to store the value of the read
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* @eeprom_id: the ID of the EEPROM
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* @addrmode: how the EEPROM is to be accessed
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*
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* Returns SUCCESS or FAILURE
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*/
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int EepromReadByte(struct et131x_adapter *etdev, u32 addr, u8 *pdata)
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{
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struct pci_dev *pdev = etdev->pdev;
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int index;
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int err = 0;
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u8 control;
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u8 status = 0;
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u32 dword1 = 0;
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/*
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* The following excerpt is from "Serial EEPROM HW Design
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* Specification" Version 0.92 (9/20/2004):
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*
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* Single Byte Reads
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*
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* A single byte read is similar to the single byte write, with the
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* exception of the data flow:
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*
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* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
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* bits 7,1:0 both equal to 1, at least once after reset.
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* Subsequent operations need only to check that bits 1:0 are equal
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* to 1 prior to starting a single byte read.
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*
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* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
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* and bits 1:0 both =0. Bit 5 should be set according to the type
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* of EEPROM being accessed (1=two byte addressing, 0=one byte
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* addressing).
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*
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* 3. Write the address to the LBCIF Address Register (I2C read will
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* begin).
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*
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* 4. Monitor bit 0 of the LBCIF Status Register. When =1, I2C read
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* is complete. (if bit 1 =1 and bit 0 stays =0, a hardware failure
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* has occurred).
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*
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* 5. Check bit 2 of the LBCIF Status Register. If =1, then an error
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* has occurred. The data that has been returned from the PHY may
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* be invalid.
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*
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* 6. Regardless of error status, read data byte from LBCIF Data
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* Register. If another byte is required, go to step 1.
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*/
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/* Step 1: */
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for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {
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/* Read registers grouped in DWORD1 */
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if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
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&dword1)) {
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err = 1;
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break;
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}
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status = EXTRACT_STATUS_REGISTER(dword1);
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if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
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status & LBCIF_STATUS_I2C_IDLE) {
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/* bits 1:0 are equal to 1 */
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break;
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}
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}
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if (err || (index >= MAX_NUM_REGISTER_POLLS))
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return FAILURE;
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/* Step 2: */
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control = 0;
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control |= LBCIF_CONTROL_LBCIF_ENABLE;
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if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
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control)) {
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return FAILURE;
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}
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/* Step 3: */
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if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,
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addr)) {
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return FAILURE;
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}
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/* Step 4: */
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for (index = 0; index < MAX_NUM_REGISTER_POLLS; index++) {
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/* Read registers grouped in DWORD1 */
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if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
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&dword1)) {
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err = 1;
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break;
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}
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status = EXTRACT_STATUS_REGISTER(dword1);
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if (status & LBCIF_STATUS_PHY_QUEUE_AVAIL
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&& status & LBCIF_STATUS_I2C_IDLE) {
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/* I2C read complete */
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break;
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}
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}
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if (err || (index >= MAX_NUM_REGISTER_POLLS))
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return FAILURE;
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/* Step 6: */
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*pdata = EXTRACT_DATA_REGISTER(dword1);
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return (status & LBCIF_STATUS_ACK_ERROR) ? FAILURE : SUCCESS;
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}
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