4508dc21fe
Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
884 lines
17 KiB
ArmAsm
884 lines
17 KiB
ArmAsm
/*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <asm/errno.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/cputable.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#ifdef CONFIG_8xx
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#define ISYNC_8xx isync
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#else
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#define ISYNC_8xx
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#endif
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.text
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.align 5
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_GLOBAL(__delay)
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cmpwi 0,r3,0
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mtctr r3
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beqlr
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1: bdnz 1b
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blr
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/*
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* Returns (address we're running at) - (address we were linked at)
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* for use before the text and data are mapped to KERNELBASE.
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*/
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_GLOBAL(reloc_offset)
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mflr r0
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bl 1f
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1: mflr r3
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r3,r4,r3
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mtlr r0
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blr
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/*
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* add_reloc_offset(x) returns x + reloc_offset().
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*/
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_GLOBAL(add_reloc_offset)
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mflr r0
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bl 1f
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1: mflr r5
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r5,r4,r5
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add r3,r3,r5
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mtlr r0
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blr
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/*
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* sub_reloc_offset(x) returns x - reloc_offset().
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*/
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_GLOBAL(sub_reloc_offset)
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mflr r0
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bl 1f
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1: mflr r5
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r5,r4,r5
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subf r3,r5,r3
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mtlr r0
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blr
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/*
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* reloc_got2 runs through the .got2 section adding an offset
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* to each entry.
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*/
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_GLOBAL(reloc_got2)
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mflr r11
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lis r7,__got2_start@ha
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addi r7,r7,__got2_start@l
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lis r8,__got2_end@ha
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addi r8,r8,__got2_end@l
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subf r8,r7,r8
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srwi. r8,r8,2
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beqlr
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mtctr r8
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bl 1f
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1: mflr r0
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r0,r4,r0
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add r7,r0,r7
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2: lwz r0,0(r7)
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add r0,r0,r3
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stw r0,0(r7)
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addi r7,r7,4
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bdnz 2b
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mtlr r11
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blr
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/*
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* call_setup_cpu - call the setup_cpu function for this cpu
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* r3 = data offset, r24 = cpu number
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*
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* Setup function is called with:
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* r3 = data offset
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* r4 = ptr to CPU spec (relocated)
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*/
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_GLOBAL(call_setup_cpu)
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addis r4,r3,cur_cpu_spec@ha
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addi r4,r4,cur_cpu_spec@l
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lwz r4,0(r4)
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add r4,r4,r3
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lwz r5,CPU_SPEC_SETUP(r4)
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cmpi 0,r5,0
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add r5,r5,r3
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beqlr
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mtctr r5
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bctr
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/*
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* complement mask on the msr then "or" some values on.
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* _nmask_and_or_msr(nmask, value_to_or)
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*/
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_GLOBAL(_nmask_and_or_msr)
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mfmsr r0 /* Get current msr */
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andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
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or r0,r0,r4 /* Or on the bits in r4 (second parm) */
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SYNC /* Some chip revs have problems here... */
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mtmsr r0 /* Update machine state */
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isync
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blr /* Done */
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/*
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* Flush MMU TLB
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*/
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_GLOBAL(_tlbia)
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#if defined(CONFIG_40x)
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sync /* Flush to memory before changing mapping */
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tlbia
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isync /* Flush shadow TLB */
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#elif defined(CONFIG_44x)
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li r3,0
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sync
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/* Load high watermark */
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lis r4,tlb_44x_hwater@ha
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lwz r5,tlb_44x_hwater@l(r4)
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1: tlbwe r3,r3,PPC44x_TLB_PAGEID
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addi r3,r3,1
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cmpw 0,r3,r5
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ble 1b
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isync
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#elif defined(CONFIG_FSL_BOOKE)
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/* Invalidate all entries in TLB0 */
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li r3, 0x04
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tlbivax 0,3
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/* Invalidate all entries in TLB1 */
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li r3, 0x0c
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tlbivax 0,3
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/* Invalidate all entries in TLB2 */
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li r3, 0x14
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tlbivax 0,3
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/* Invalidate all entries in TLB3 */
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li r3, 0x1c
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tlbivax 0,3
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msync
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#ifdef CONFIG_SMP
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tlbsync
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#endif /* CONFIG_SMP */
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#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,18
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lwz r8,TI_CPU(r8)
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oris r8,r8,10
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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sync
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tlbia
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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sync
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tlbia
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sync
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#endif /* CONFIG_SMP */
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#endif /* ! defined(CONFIG_40x) */
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blr
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/*
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* Flush MMU TLB for a particular address
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*/
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_GLOBAL(_tlbie)
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#if defined(CONFIG_40x)
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tlbsx. r3, 0, r3
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bne 10f
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sync
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/* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
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* Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
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* the TLB entry. */
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tlbwe r3, r3, TLB_TAG
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isync
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10:
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#elif defined(CONFIG_44x)
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mfspr r4,SPRN_MMUCR
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mfspr r5,SPRN_PID /* Get PID */
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rlwimi r4,r5,0,24,31 /* Set TID */
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mtspr SPRN_MMUCR,r4
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tlbsx. r3, 0, r3
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bne 10f
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sync
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/* There are only 64 TLB entries, so r3 < 64,
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* which means bit 22, is clear. Since 22 is
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* the V bit in the TLB_PAGEID, loading this
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* value will invalidate the TLB entry.
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*/
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tlbwe r3, r3, PPC44x_TLB_PAGEID
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isync
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10:
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#elif defined(CONFIG_FSL_BOOKE)
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rlwinm r4, r3, 0, 0, 19
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ori r5, r4, 0x08 /* TLBSEL = 1 */
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ori r6, r4, 0x10 /* TLBSEL = 2 */
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ori r7, r4, 0x18 /* TLBSEL = 3 */
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tlbivax 0, r4
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tlbivax 0, r5
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tlbivax 0, r6
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tlbivax 0, r7
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msync
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#if defined(CONFIG_SMP)
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tlbsync
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#endif /* CONFIG_SMP */
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#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,18
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lwz r8,TI_CPU(r8)
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oris r8,r8,11
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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eieio
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tlbie r3
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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tlbie r3
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sync
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#endif /* CONFIG_SMP */
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#endif /* ! CONFIG_40x */
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blr
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/*
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* Flush instruction cache.
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* This is a no-op on the 601.
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*/
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_GLOBAL(flush_instruction_cache)
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#if defined(CONFIG_8xx)
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isync
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lis r5, IDC_INVALL@h
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mtspr SPRN_IC_CST, r5
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#elif defined(CONFIG_4xx)
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#ifdef CONFIG_403GCX
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li r3, 512
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mtctr r3
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lis r4, KERNELBASE@h
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1: iccci 0, r4
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addi r4, r4, 16
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bdnz 1b
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#else
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lis r3, KERNELBASE@h
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iccci 0,r3
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#endif
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#elif CONFIG_FSL_BOOKE
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BEGIN_FTR_SECTION
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mfspr r3,SPRN_L1CSR0
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ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
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/* msync; isync recommended here */
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mtspr SPRN_L1CSR0,r3
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isync
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blr
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END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
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mfspr r3,SPRN_L1CSR1
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ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
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mtspr SPRN_L1CSR1,r3
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#else
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mfspr r3,SPRN_PVR
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rlwinm r3,r3,16,16,31
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cmpwi 0,r3,1
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beqlr /* for 601, do nothing */
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/* 603/604 processor - use invalidate-all bit in HID0 */
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mfspr r3,SPRN_HID0
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ori r3,r3,HID0_ICFI
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mtspr SPRN_HID0,r3
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#endif /* CONFIG_8xx/4xx */
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isync
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blr
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/*
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* Write any modified data cache blocks out to memory
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* and invalidate the corresponding instruction cache blocks.
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* This is a no-op on the 601.
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*
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* __flush_icache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(__flush_icache_range)
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BEGIN_FTR_SECTION
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blr /* for 601, do nothing */
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END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,L1_CACHE_BYTES
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bdnz 2b
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sync /* additional sync needed on g4 */
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isync
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blr
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/*
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* Write any modified data cache blocks out to memory.
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* Does not invalidate the corresponding cache lines (especially for
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* any corresponding instruction cache).
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*
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* clean_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(clean_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbst 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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blr
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/*
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* Write any modified data cache blocks out to memory and invalidate them.
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* Does not invalidate the corresponding instruction cache blocks.
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*
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* flush_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbf 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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blr
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/*
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* Like above, but invalidate the D-cache. This is used by the 8xx
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* to invalidate the cache so the PPC core doesn't get stale data
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* from the CPM (no cache snooping here :-).
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*
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* invalidate_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(invalidate_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbi 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbi's to get to ram */
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blr
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#ifdef CONFIG_NOT_COHERENT_CACHE
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/*
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* 40x cores have 8K or 16K dcache and 32 byte line size.
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* 44x has a 32K dcache and 32 byte line size.
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* 8xx has 1, 2, 4, 8K variants.
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* For now, cover the worst case of the 44x.
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* Must be called with external interrupts disabled.
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*/
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#define CACHE_NWAYS 64
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#define CACHE_NLINES 16
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_GLOBAL(flush_dcache_all)
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li r4, (2 * CACHE_NWAYS * CACHE_NLINES)
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mtctr r4
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lis r5, KERNELBASE@h
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1: lwz r3, 0(r5) /* Load one word from every line */
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addi r5, r5, L1_CACHE_BYTES
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bdnz 1b
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blr
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#endif /* CONFIG_NOT_COHERENT_CACHE */
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/*
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* Flush a particular page from the data cache to RAM.
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* Note: this is necessary because the instruction cache does *not*
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* snoop from the data cache.
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* This is a no-op on the 601 which has a unified cache.
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*
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* void __flush_dcache_icache(void *page)
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*/
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_GLOBAL(__flush_dcache_icache)
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BEGIN_FTR_SECTION
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blr /* for 601, do nothing */
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END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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rlwinm r3,r3,0,0,19 /* Get page base address */
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li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
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mtctr r4
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mr r6,r3
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0: dcbst 0,r3 /* Write line to ram */
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addi r3,r3,L1_CACHE_BYTES
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bdnz 0b
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sync
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mtctr r4
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1: icbi 0,r6
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addi r6,r6,L1_CACHE_BYTES
|
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bdnz 1b
|
|
sync
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Flush a particular page from the data cache to RAM, identified
|
|
* by its physical address. We turn off the MMU so we can just use
|
|
* the physical address (this may be a highmem page without a kernel
|
|
* mapping).
|
|
*
|
|
* void __flush_dcache_icache_phys(unsigned long physaddr)
|
|
*/
|
|
_GLOBAL(__flush_dcache_icache_phys)
|
|
BEGIN_FTR_SECTION
|
|
blr /* for 601, do nothing */
|
|
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
|
|
mfmsr r10
|
|
rlwinm r0,r10,0,28,26 /* clear DR */
|
|
mtmsr r0
|
|
isync
|
|
rlwinm r3,r3,0,0,19 /* Get page base address */
|
|
li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
|
|
mtctr r4
|
|
mr r6,r3
|
|
0: dcbst 0,r3 /* Write line to ram */
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 0b
|
|
sync
|
|
mtctr r4
|
|
1: icbi 0,r6
|
|
addi r6,r6,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync
|
|
mtmsr r10 /* restore DR */
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Clear pages using the dcbz instruction, which doesn't cause any
|
|
* memory traffic (except to write out any cache lines which get
|
|
* displaced). This only works on cacheable memory.
|
|
*
|
|
* void clear_pages(void *page, int order) ;
|
|
*/
|
|
_GLOBAL(clear_pages)
|
|
li r0,4096/L1_CACHE_BYTES
|
|
slw r0,r0,r4
|
|
mtctr r0
|
|
#ifdef CONFIG_8xx
|
|
li r4, 0
|
|
1: stw r4, 0(r3)
|
|
stw r4, 4(r3)
|
|
stw r4, 8(r3)
|
|
stw r4, 12(r3)
|
|
#else
|
|
1: dcbz 0,r3
|
|
#endif
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
blr
|
|
|
|
/*
|
|
* Copy a whole page. We use the dcbz instruction on the destination
|
|
* to reduce memory traffic (it eliminates the unnecessary reads of
|
|
* the destination into cache). This requires that the destination
|
|
* is cacheable.
|
|
*/
|
|
#define COPY_16_BYTES \
|
|
lwz r6,4(r4); \
|
|
lwz r7,8(r4); \
|
|
lwz r8,12(r4); \
|
|
lwzu r9,16(r4); \
|
|
stw r6,4(r3); \
|
|
stw r7,8(r3); \
|
|
stw r8,12(r3); \
|
|
stwu r9,16(r3)
|
|
|
|
_GLOBAL(copy_page)
|
|
addi r3,r3,-4
|
|
addi r4,r4,-4
|
|
|
|
#ifdef CONFIG_8xx
|
|
/* don't use prefetch on 8xx */
|
|
li r0,4096/L1_CACHE_BYTES
|
|
mtctr r0
|
|
1: COPY_16_BYTES
|
|
bdnz 1b
|
|
blr
|
|
|
|
#else /* not 8xx, we can prefetch */
|
|
li r5,4
|
|
|
|
#if MAX_COPY_PREFETCH > 1
|
|
li r0,MAX_COPY_PREFETCH
|
|
li r11,4
|
|
mtctr r0
|
|
11: dcbt r11,r4
|
|
addi r11,r11,L1_CACHE_BYTES
|
|
bdnz 11b
|
|
#else /* MAX_COPY_PREFETCH == 1 */
|
|
dcbt r5,r4
|
|
li r11,L1_CACHE_BYTES+4
|
|
#endif /* MAX_COPY_PREFETCH */
|
|
li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
|
|
crclr 4*cr0+eq
|
|
2:
|
|
mtctr r0
|
|
1:
|
|
dcbt r11,r4
|
|
dcbz r5,r3
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 32
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 64
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 128
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
#endif
|
|
#endif
|
|
#endif
|
|
bdnz 1b
|
|
beqlr
|
|
crnot 4*cr0+eq,4*cr0+eq
|
|
li r0,MAX_COPY_PREFETCH
|
|
li r11,4
|
|
b 2b
|
|
#endif /* CONFIG_8xx */
|
|
|
|
/*
|
|
* void atomic_clear_mask(atomic_t mask, atomic_t *addr)
|
|
* void atomic_set_mask(atomic_t mask, atomic_t *addr);
|
|
*/
|
|
_GLOBAL(atomic_clear_mask)
|
|
10: lwarx r5,0,r4
|
|
andc r5,r5,r3
|
|
PPC405_ERR77(0,r4)
|
|
stwcx. r5,0,r4
|
|
bne- 10b
|
|
blr
|
|
_GLOBAL(atomic_set_mask)
|
|
10: lwarx r5,0,r4
|
|
or r5,r5,r3
|
|
PPC405_ERR77(0,r4)
|
|
stwcx. r5,0,r4
|
|
bne- 10b
|
|
blr
|
|
|
|
/*
|
|
* I/O string operations
|
|
*
|
|
* insb(port, buf, len)
|
|
* outsb(port, buf, len)
|
|
* insw(port, buf, len)
|
|
* outsw(port, buf, len)
|
|
* insl(port, buf, len)
|
|
* outsl(port, buf, len)
|
|
* insw_ns(port, buf, len)
|
|
* outsw_ns(port, buf, len)
|
|
* insl_ns(port, buf, len)
|
|
* outsl_ns(port, buf, len)
|
|
*
|
|
* The *_ns versions don't do byte-swapping.
|
|
*/
|
|
_GLOBAL(_insb)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,1
|
|
blelr-
|
|
00: lbz r5,0(r3)
|
|
01: eieio
|
|
02: stbu r5,1(r4)
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(_outsb)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,1
|
|
blelr-
|
|
00: lbzu r5,1(r4)
|
|
01: stb r5,0(r3)
|
|
02: eieio
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(_insw_ns)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,2
|
|
blelr-
|
|
00: lhz r5,0(r3)
|
|
01: eieio
|
|
02: sthu r5,2(r4)
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(_outsw_ns)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,2
|
|
blelr-
|
|
00: lhzu r5,2(r4)
|
|
01: sth r5,0(r3)
|
|
02: eieio
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(_insl_ns)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,4
|
|
blelr-
|
|
00: lwz r5,0(r3)
|
|
01: eieio
|
|
02: stwu r5,4(r4)
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
_GLOBAL(_outsl_ns)
|
|
cmpwi 0,r5,0
|
|
mtctr r5
|
|
subi r4,r4,4
|
|
blelr-
|
|
00: lwzu r5,4(r4)
|
|
01: stw r5,0(r3)
|
|
02: eieio
|
|
ISYNC_8xx
|
|
.section .fixup,"ax"
|
|
03: blr
|
|
.text
|
|
.section __ex_table, "a"
|
|
.align 2
|
|
.long 00b, 03b
|
|
.long 01b, 03b
|
|
.long 02b, 03b
|
|
.text
|
|
bdnz 00b
|
|
blr
|
|
|
|
/*
|
|
* Extended precision shifts.
|
|
*
|
|
* Updated to be valid for shift counts from 0 to 63 inclusive.
|
|
* -- Gabriel
|
|
*
|
|
* R3/R4 has 64 bit value
|
|
* R5 has shift count
|
|
* result in R3/R4
|
|
*
|
|
* ashrdi3: arithmetic right shift (sign propagation)
|
|
* lshrdi3: logical right shift
|
|
* ashldi3: left shift
|
|
*/
|
|
_GLOBAL(__ashrdi3)
|
|
subfic r6,r5,32
|
|
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
|
|
rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
|
|
sraw r7,r3,r7 # t2 = MSW >> (count-32)
|
|
or r4,r4,r6 # LSW |= t1
|
|
slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
|
|
sraw r3,r3,r5 # MSW = MSW >> count
|
|
or r4,r4,r7 # LSW |= t2
|
|
blr
|
|
|
|
_GLOBAL(__ashldi3)
|
|
subfic r6,r5,32
|
|
slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
|
|
slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
|
|
or r3,r3,r6 # MSW |= t1
|
|
slw r4,r4,r5 # LSW = LSW << count
|
|
or r3,r3,r7 # MSW |= t2
|
|
blr
|
|
|
|
_GLOBAL(__lshrdi3)
|
|
subfic r6,r5,32
|
|
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
|
|
srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
|
|
or r4,r4,r6 # LSW |= t1
|
|
srw r3,r3,r5 # MSW = MSW >> count
|
|
or r4,r4,r7 # LSW |= t2
|
|
blr
|
|
|
|
_GLOBAL(abs)
|
|
srawi r4,r3,31
|
|
xor r3,r3,r4
|
|
sub r3,r3,r4
|
|
blr
|
|
|
|
_GLOBAL(_get_SP)
|
|
mr r3,r1 /* Close enough */
|
|
blr
|
|
|
|
/*
|
|
* Create a kernel thread
|
|
* kernel_thread(fn, arg, flags)
|
|
*/
|
|
_GLOBAL(kernel_thread)
|
|
stwu r1,-16(r1)
|
|
stw r30,8(r1)
|
|
stw r31,12(r1)
|
|
mr r30,r3 /* function */
|
|
mr r31,r4 /* argument */
|
|
ori r3,r5,CLONE_VM /* flags */
|
|
oris r3,r3,CLONE_UNTRACED>>16
|
|
li r4,0 /* new sp (unused) */
|
|
li r0,__NR_clone
|
|
sc
|
|
cmpwi 0,r3,0 /* parent or child? */
|
|
bne 1f /* return if parent */
|
|
li r0,0 /* make top-level stack frame */
|
|
stwu r0,-16(r1)
|
|
mtlr r30 /* fn addr in lr */
|
|
mr r3,r31 /* load arg and call fn */
|
|
PPC440EP_ERR42
|
|
blrl
|
|
li r0,__NR_exit /* exit if function returns */
|
|
li r3,0
|
|
sc
|
|
1: lwz r30,8(r1)
|
|
lwz r31,12(r1)
|
|
addi r1,r1,16
|
|
blr
|
|
|
|
_GLOBAL(kernel_execve)
|
|
li r0,__NR_execve
|
|
sc
|
|
bnslr
|
|
neg r3,r3
|
|
blr
|
|
|
|
/*
|
|
* This routine is just here to keep GCC happy - sigh...
|
|
*/
|
|
_GLOBAL(__main)
|
|
blr
|
|
|