1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
365 lines
12 KiB
C
365 lines
12 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
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*
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* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
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* Copyright (C) 1999 by Ralf Baechle
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*/
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#ifndef _ASM_SN_SN0_ADDRS_H
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#define _ASM_SN_SN0_ADDRS_H
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#include <linux/config.h>
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/*
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* SN0 (on a T5) Address map
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*
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* This file contains a set of definitions and macros which are used
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* to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
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* and UNCAC) used by the SN0 architecture. It also contains addresses
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* for "major" statically locatable PROM/Kernel data structures, such as
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* the partition table, the configuration data structure, etc.
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* We make an implicit assumption that the processor using this file
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* follows the R10K's provisions for specifying uncached attributes;
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* should this change, the base registers may very well become processor-
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* dependent.
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*
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* For more information on the address spaces, see the "Local Resources"
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* chapter of the Hub specification.
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*
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* NOTE: This header file is included both by C and by assembler source
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* files. Please bracket any language-dependent definitions
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* appropriately.
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*/
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/*
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* Some of the macros here need to be casted to appropriate types when used
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* from C. They definitely must not be casted from assembly language so we
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* use some new ANSI preprocessor stuff to paste these on where needed.
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*/
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/*
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* The following couple of definitions will eventually need to be variables,
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* since the amount of address space assigned to each node depends on
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* whether the system is running in N-mode (more nodes with less memory)
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* or M-mode (fewer nodes with more memory). We expect that it will
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* be a while before we need to make this decision dynamically, though,
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* so for now we just use defines bracketed by an ifdef.
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*/
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#ifdef CONFIG_SGI_SN0_N_MODE
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#define NODE_SIZE_BITS 31
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#define BWIN_SIZE_BITS 28
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#define NASID_BITS 9
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#define NASID_BITMASK (0x1ffLL)
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#define NASID_SHFT 31
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#define NASID_META_BITS 5
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#define NASID_LOCAL_BITS 4
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#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
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#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
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#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */
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#define NODE_SIZE_BITS 32
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#define BWIN_SIZE_BITS 29
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#define NASID_BITMASK (0xffLL)
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#define NASID_BITS 8
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#define NASID_SHFT 32
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#define NASID_META_BITS 4
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#define NASID_LOCAL_BITS 4
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#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
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#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
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#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */
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#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS)
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#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT)
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#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \
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NASID_SHFT) & NASID_BITMASK)
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#if !defined(__ASSEMBLY__) && !defined(_STANDALONE)
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#define NODE_SWIN_BASE(nasid, widget) \
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((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
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: RAW_NODE_SWIN_BASE(nasid, widget))
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#else /* __ASSEMBLY__ || _STANDALONE */
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#define NODE_SWIN_BASE(nasid, widget) \
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(NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
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#endif /* __ASSEMBLY__ || _STANDALONE */
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/*
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* The following definitions pertain to the IO special address
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* space. They define the location of the big and little windows
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* of any given node.
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*/
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#define BWIN_INDEX_BITS 3
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#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS)
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#define BWIN_SIZEMASK (BWIN_SIZE - 1)
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#define BWIN_WIDGET_MASK 0x7
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#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
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#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
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(UINT64_CAST (bigwin) << BWIN_SIZE_BITS))
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#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
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#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
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/*
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* Verify if addr belongs to large window address of node with "nasid"
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*
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*
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* NOTE: "addr" is expected to be XKPHYS address, and NOT physical
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* address
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*
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*
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*/
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#define NODE_BWIN_ADDR(nasid, addr) \
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(((addr) >= NODE_BWIN_BASE0(nasid)) && \
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((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
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BWIN_SIZE)))
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/*
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* The following define the major position-independent aliases used
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* in SN0.
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* CALIAS -- Varies in size, points to the first n bytes of memory
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* on the reader's node.
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*/
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#define CALIAS_BASE CAC_BASE
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#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \
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((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
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#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))
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/* Turn on sable logging for the processors whose bits are set. */
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#ifdef SABLE
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#define SABLE_LOG_TRIGGER(_map) \
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*((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map)
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#else
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#define SABLE_LOG_TRIGGER(_map)
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#endif /* SABLE */
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#ifndef __ASSEMBLY__
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#define KERN_NMI_ADDR(nasid, slice) \
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TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \
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(IP27_NMI_KREGS_CPU_SIZE * (slice)))
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#endif /* !__ASSEMBLY__ */
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#ifdef PROM
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#define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
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#define MISC_PROM_SIZE 0x200000
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#define DIAG_BASE PHYS_TO_K0(0x01500000)
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#define DIAG_SIZE 0x300000
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#define ROUTE_BASE PHYS_TO_K0(0x01800000)
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#define ROUTE_SIZE 0x200000
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#define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000)
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#define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000)
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#define IP27PROM_CORP_MAX 32
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#define IP27PROM_CORP PHYS_TO_K0(0x01800000)
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#define IP27PROM_CORP_SIZE 0x10000
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#define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000)
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#define IP27PROM_CORP_STKSIZE 0x2000
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#define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000)
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#define IP27PROM_DECOMP_SIZE 0xfff00
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#define IP27PROM_BASE PHYS_TO_K0(0x01a00000)
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#define IP27PROM_BASE_MAPPED (UNCAC_BASE | 0x1fc00000)
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#define IP27PROM_SIZE_MAX 0x100000
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#define IP27PROM_PCFG PHYS_TO_K0(0x01b00000)
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#define IP27PROM_PCFG_SIZE 0xd0000
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#define IP27PROM_ERRDMP PHYS_TO_K1(0x01bd0000)
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#define IP27PROM_ERRDMP_SIZE 0xf000
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#define IP27PROM_INIT_START PHYS_TO_K1(0x01bd0000)
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#define IP27PROM_CONSOLE PHYS_TO_K1(0x01bdf000)
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#define IP27PROM_CONSOLE_SIZE 0x200
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#define IP27PROM_NETUART PHYS_TO_K1(0x01bdf200)
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#define IP27PROM_NETUART_SIZE 0x100
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#define IP27PROM_UNUSED1 PHYS_TO_K1(0x01bdf300)
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#define IP27PROM_UNUSED1_SIZE 0x500
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#define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x01bdf800)
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#define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x01bdfc00)
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#define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000)
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#define IP27PROM_STACK_B PHYS_TO_K0(0x01bf0000)
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#define IP27PROM_STACK_SHFT 16
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#define IP27PROM_STACK_SIZE (1 << IP27PROM_STACK_SHFT)
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#define IP27PROM_INIT_END PHYS_TO_K0(0x01c00000)
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#define SLAVESTACK_BASE PHYS_TO_K0(0x01580000)
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#define SLAVESTACK_SIZE 0x40000
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#define ENETBUFS_BASE PHYS_TO_K0(0x01f80000)
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#define ENETBUFS_SIZE 0x20000
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#define IO6PROM_BASE PHYS_TO_K0(0x01c00000)
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#define IO6PROM_SIZE 0x400000
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#define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000)
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#define IO6DPROM_BASE PHYS_TO_K0(0x01c00000)
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#define IO6DPROM_SIZE 0x200000
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#define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000)
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#define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000)
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#define IP27PROM_INT_LAUNCH 10 /* and 11 */
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#define IP27PROM_INT_NETUART 12 /* through 17 */
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#endif /* PROM */
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/*
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* needed by symmon so it needs to be outside #if PROM
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*/
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#define IP27PROM_ELSC_SHFT 10
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#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT)
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/*
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* This address is used by IO6PROM to build MemoryDescriptors of
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* free memory. This address is important since unix gets loaded
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* at this address, and this memory has to be FREE if unix is to
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* be loaded.
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*/
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#define FREEMEM_BASE PHYS_TO_K0(0x2000000)
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#define IO6PROM_STACK_SHFT 14 /* stack per cpu */
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#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT)
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/*
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* IP27 PROM vectors
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*/
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#define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000)
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#define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008)
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#define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010)
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#define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018)
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#define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020)
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#define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028)
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#define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030)
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#define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038)
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#define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040)
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#define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048)
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#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0) /* base of UART regs */
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#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0) /* UART command reg */
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#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */
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#define KL_I2C_REG MD_UREG0_0 /* I2C reg */
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#ifndef __ASSEMBLY__
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/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
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* CACHE_ERR_SP_PTR could either contain an address to the stack, or
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* the stack could start at CACHE_ERR_SP_PTR
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*/
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#if defined (HUB_ERR_STS_WAR)
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#define CACHE_ERR_EFRAME 0x480
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#else /* HUB_ERR_STS_WAR */
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#define CACHE_ERR_EFRAME 0x400
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#endif /* HUB_ERR_STS_WAR */
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#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE)
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#define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */
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#define CACHE_ERR_IBASE_PTR (0x1000 - 40)
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#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16)
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#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
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#endif /* !__ASSEMBLY__ */
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#define _ARCSPROM
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#ifdef _STANDALONE
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/*
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* The PROM needs to pass the device base address and the
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* device pci cfg space address to the device drivers during
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* install. The COMPONENT->Key field is used for this purpose.
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* Macros needed by SN0 device drivers to convert the
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* COMPONENT->Key field to the respective base address.
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* Key field looks as follows:
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*
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* +----------------------------------------------------+
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* |devnasid | widget |pciid |hubwidid|hstnasid | adap |
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* | 2 | 1 | 1 | 1 | 2 | 1 |
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* +----------------------------------------------------+
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* | | | | | | |
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* 64 48 40 32 24 8 0
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*
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* These are used by standalone drivers till the io infrastructure
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* is in place.
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*/
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#ifndef __ASSEMBLY__
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#define uchar unsigned char
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#define KEY_DEVNASID_SHFT 48
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#define KEY_WIDID_SHFT 40
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#define KEY_PCIID_SHFT 32
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#define KEY_HUBWID_SHFT 24
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#define KEY_HSTNASID_SHFT 8
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#define MK_SN0_KEY(nasid, widid, pciid) \
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((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
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((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
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((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
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#define ADD_HUBWID_KEY(key,hubwid)\
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(key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
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#define ADD_HSTNASID_KEY(key,hstnasid)\
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(key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
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#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT))
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#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT))
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#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT))
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#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT))
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#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT))
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#define PCI_64_TARGID_SHFT 60
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#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
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GET_WIDID_FROM_KEY(key))\
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| BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
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#define GET_PCICFGBASE_FROM_KEY(key) \
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(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
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GET_WIDID_FROM_KEY(key))\
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| BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
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#define GET_WIDBASE_FROM_KEY(key) \
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(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
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GET_WIDID_FROM_KEY(key)))
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#define PUT_INSTALL_STATUS(c,s) c->Revision = s
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#define GET_INSTALL_STATUS(c) c->Revision
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#endif /* !__ASSEMBLY__ */
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#endif /* _STANDALONE */
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#if defined (HUB_ERR_STS_WAR)
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#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
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#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR)
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#define ERR_STS_WAR_PHYSADDR TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
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/* Used to match addr in error reg. */
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#define OLD_ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
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#endif /* HUB_ERR_STS_WAR */
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#endif /* _ASM_SN_SN0_ADDRS_H */
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