5e6a5845dd
- new driver: gpio-virtio allowing a guest VM running linux to access GPIO lines provided by the host - split the GPIO driver out of the rockchip pin control driver - add support for a new model to gpio-aspeed-sgpio, refactor the driver and use generic device property interfaces, improve property sanitization - add ACPI support to gpio-tegra186 - improve the code setting the line names to support multiple GPIO banks per device - constify a bunch of OF functions in the core GPIO code and make the declaration for one of the core OF functions we use consistent within its header - use software nodes in intel_quark_i2c_gpio - add support for the gpio-line-names property in gpio-mt7621 - use the standard GPIO function for setting the GPIO names in gpio-brcmstb - fix a bunch of leaks and other bugs in gpio-mpc8xxx - use generic pm callbacks in gpio-ml-ioh - improve resource management and PM handling in gpio-mlxbf2 - modernize and improve the gpio-dwapb driver - coding style improvements in gpio-rcar - documentation fixes and improvements - update the MAINTAINERS entry for gpio-zynq - minor tweaks in several drivers -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEFp3rbAvDxGAT0sefEacuoBRx13IFAmE3ItgACgkQEacuoBRx 13LKqA//Q2E9QYJx0lLO0C15JKzJjqYGyVqSm73Huo8pKWRSKr9YuB4/tBPKz5Ya pg/h7wbsk+mtQ0pqot/SEGVLo1rK6ZcPiCDkYkuaVsY9pS0zX7A/Sb2N7xKML+Nj wTFuhSZH2byxH6QgUrX3RLMagW4p/owlDvFjZ6Z6Vh8Ulsnb0pdL3nYg5L017GMT A1ySzbP79NK3LfOLTqdqgALv4EF2x+paolyEpI/Jv0naBYkIP4AcbOBQEVMpoCY/ XEcIdPvqMyPm4PdYSy3iCqtkf7jclDbV030SHlir2bKHjI79l8ARy0Tu6hvISRSG 8XMwt6ke40GYnPkESZTkWlqeVHYzli84FxYXYLnqFa/21c4qswHk/aZZq5h83fn8 7aonkEQQuHfQM00MvLu0mhtKXYdLbqv7jjd0CYChwxQSpu0iu7IQSWW8c2YmGvvt vqfM8TdKyGNPAmSl2/enPKOr+LugG4rcgMehU9/p6QvHbB6y2SxC1MykldPOdC6d 53PeDeNP6XOp2s10zVPWh6P0rbrMaEtv/GZ143kUw9bhb1g3woX5SaS7W76cOXhE kty6g1e8xNaKDZbJ++UAh7G9IGQdtz0xRCXDUHFUc89uCThc9RcHowNPtzMMnmgM ucWJ81XnGDSDyzzG/f7uhcOtszWYCOtFmteooaMGB36/pH2CG9Y= =y/RY -----END PGP SIGNATURE----- Merge tag 'gpio-updates-for-v5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux Pull gpio updates from Bartosz Golaszewski: "We mostly have various improvements and refactoring all over the place but also some interesting new features - like the virtio GPIO driver that allows guest VMs to use host's GPIOs. We also have a new/old GPIO driver for rockchip - this one has been split out of the pinctrl driver. Summary: - new driver: gpio-virtio allowing a guest VM running linux to access GPIO lines provided by the host - split the GPIO driver out of the rockchip pin control driver - add support for a new model to gpio-aspeed-sgpio, refactor the driver and use generic device property interfaces, improve property sanitization - add ACPI support to gpio-tegra186 - improve the code setting the line names to support multiple GPIO banks per device - constify a bunch of OF functions in the core GPIO code and make the declaration for one of the core OF functions we use consistent within its header - use software nodes in intel_quark_i2c_gpio - add support for the gpio-line-names property in gpio-mt7621 - use the standard GPIO function for setting the GPIO names in gpio-brcmstb - fix a bunch of leaks and other bugs in gpio-mpc8xxx - use generic pm callbacks in gpio-ml-ioh - improve resource management and PM handling in gpio-mlxbf2 - modernize and improve the gpio-dwapb driver - coding style improvements in gpio-rcar - documentation fixes and improvements - update the MAINTAINERS entry for gpio-zynq - minor tweaks in several drivers" * tag 'gpio-updates-for-v5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (35 commits) gpio: mpc8xxx: Use 'devm_gpiochip_add_data()' to simplify the code and avoid a leak gpio: mpc8xxx: Fix a potential double iounmap call in 'mpc8xxx_probe()' gpio: mpc8xxx: Fix a resources leak in the error handling path of 'mpc8xxx_probe()' gpio: viperboard: remove platform_set_drvdata() call in probe gpio: virtio: Add missing mailings lists in MAINTAINERS entry gpio: virtio: Fix sparse warnings gpio: remove the obsolete MX35 3DS BOARD MC9S08DZ60 GPIO functions gpio: max730x: Use the right include gpio: Add virtio-gpio driver gpio: mlxbf2: Use DEFINE_RES_MEM_NAMED() helper macro gpio: mlxbf2: Use devm_platform_ioremap_resource() gpio: mlxbf2: Drop wrong use of ACPI_PTR() gpio: mlxbf2: Convert to device PM ops gpio: dwapb: Get rid of legacy platform data mfd: intel_quark_i2c_gpio: Convert GPIO to use software nodes gpio: dwapb: Read GPIO base from gpio-base property gpio: dwapb: Unify ACPI enumeration checks in get_irq() and configure_irqs() gpiolib: Deduplicate forward declaration in the consumer.h header MAINTAINERS: update gpio-zynq.yaml reference gpio: tegra186: Add ACPI support ...
459 lines
12 KiB
C
459 lines
12 KiB
C
/*
|
||
* GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
|
||
*
|
||
* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
|
||
* Copyright (C) 2016 Freescale Semiconductor Inc.
|
||
*
|
||
* This file is licensed under the terms of the GNU General Public License
|
||
* version 2. This program is licensed "as is" without any warranty of any
|
||
* kind, whether express or implied.
|
||
*/
|
||
|
||
#include <linux/acpi.h>
|
||
#include <linux/kernel.h>
|
||
#include <linux/init.h>
|
||
#include <linux/spinlock.h>
|
||
#include <linux/io.h>
|
||
#include <linux/of.h>
|
||
#include <linux/of_gpio.h>
|
||
#include <linux/of_address.h>
|
||
#include <linux/of_irq.h>
|
||
#include <linux/of_platform.h>
|
||
#include <linux/property.h>
|
||
#include <linux/mod_devicetable.h>
|
||
#include <linux/slab.h>
|
||
#include <linux/irq.h>
|
||
#include <linux/gpio/driver.h>
|
||
#include <linux/bitops.h>
|
||
#include <linux/interrupt.h>
|
||
|
||
#define MPC8XXX_GPIO_PINS 32
|
||
|
||
#define GPIO_DIR 0x00
|
||
#define GPIO_ODR 0x04
|
||
#define GPIO_DAT 0x08
|
||
#define GPIO_IER 0x0c
|
||
#define GPIO_IMR 0x10
|
||
#define GPIO_ICR 0x14
|
||
#define GPIO_ICR2 0x18
|
||
#define GPIO_IBE 0x18
|
||
|
||
struct mpc8xxx_gpio_chip {
|
||
struct gpio_chip gc;
|
||
void __iomem *regs;
|
||
raw_spinlock_t lock;
|
||
|
||
int (*direction_output)(struct gpio_chip *chip,
|
||
unsigned offset, int value);
|
||
|
||
struct irq_domain *irq;
|
||
unsigned int irqn;
|
||
};
|
||
|
||
/*
|
||
* This hardware has a big endian bit assignment such that GPIO line 0 is
|
||
* connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
|
||
* This inline helper give the right bitmask for a certain line.
|
||
*/
|
||
static inline u32 mpc_pin2mask(unsigned int offset)
|
||
{
|
||
return BIT(31 - offset);
|
||
}
|
||
|
||
/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
|
||
* defined as output cannot be determined by reading GPDAT register,
|
||
* so we use shadow data register instead. The status of input pins
|
||
* is determined by reading GPDAT register.
|
||
*/
|
||
static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
|
||
{
|
||
u32 val;
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
|
||
u32 out_mask, out_shadow;
|
||
|
||
out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
|
||
val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
|
||
out_shadow = gc->bgpio_data & out_mask;
|
||
|
||
return !!((val | out_shadow) & mpc_pin2mask(gpio));
|
||
}
|
||
|
||
static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
|
||
unsigned int gpio, int val)
|
||
{
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
|
||
/* GPIO 28..31 are input only on MPC5121 */
|
||
if (gpio >= 28)
|
||
return -EINVAL;
|
||
|
||
return mpc8xxx_gc->direction_output(gc, gpio, val);
|
||
}
|
||
|
||
static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
|
||
unsigned int gpio, int val)
|
||
{
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
|
||
/* GPIO 0..3 are input only on MPC5125 */
|
||
if (gpio <= 3)
|
||
return -EINVAL;
|
||
|
||
return mpc8xxx_gc->direction_output(gc, gpio, val);
|
||
}
|
||
|
||
static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
|
||
{
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
|
||
|
||
if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
|
||
return irq_create_mapping(mpc8xxx_gc->irq, offset);
|
||
else
|
||
return -ENXIO;
|
||
}
|
||
|
||
static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
|
||
{
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
|
||
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
||
unsigned long mask;
|
||
int i;
|
||
|
||
mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
|
||
& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
|
||
for_each_set_bit(i, &mask, 32)
|
||
generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
|
||
|
||
return IRQ_HANDLED;
|
||
}
|
||
|
||
static void mpc8xxx_irq_unmask(struct irq_data *d)
|
||
{
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
|
||
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
||
unsigned long flags;
|
||
|
||
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
||
|
||
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
|
||
gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
|
||
| mpc_pin2mask(irqd_to_hwirq(d)));
|
||
|
||
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
||
}
|
||
|
||
static void mpc8xxx_irq_mask(struct irq_data *d)
|
||
{
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
|
||
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
||
unsigned long flags;
|
||
|
||
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
||
|
||
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
|
||
gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
|
||
& ~mpc_pin2mask(irqd_to_hwirq(d)));
|
||
|
||
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
||
}
|
||
|
||
static void mpc8xxx_irq_ack(struct irq_data *d)
|
||
{
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
|
||
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
||
|
||
gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
|
||
mpc_pin2mask(irqd_to_hwirq(d)));
|
||
}
|
||
|
||
static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
|
||
{
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
|
||
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
||
unsigned long flags;
|
||
|
||
switch (flow_type) {
|
||
case IRQ_TYPE_EDGE_FALLING:
|
||
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
||
gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
|
||
gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
|
||
| mpc_pin2mask(irqd_to_hwirq(d)));
|
||
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
||
break;
|
||
|
||
case IRQ_TYPE_EDGE_BOTH:
|
||
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
||
gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
|
||
gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
|
||
& ~mpc_pin2mask(irqd_to_hwirq(d)));
|
||
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
||
break;
|
||
|
||
default:
|
||
return -EINVAL;
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
|
||
{
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
|
||
struct gpio_chip *gc = &mpc8xxx_gc->gc;
|
||
unsigned long gpio = irqd_to_hwirq(d);
|
||
void __iomem *reg;
|
||
unsigned int shift;
|
||
unsigned long flags;
|
||
|
||
if (gpio < 16) {
|
||
reg = mpc8xxx_gc->regs + GPIO_ICR;
|
||
shift = (15 - gpio) * 2;
|
||
} else {
|
||
reg = mpc8xxx_gc->regs + GPIO_ICR2;
|
||
shift = (15 - (gpio % 16)) * 2;
|
||
}
|
||
|
||
switch (flow_type) {
|
||
case IRQ_TYPE_EDGE_FALLING:
|
||
case IRQ_TYPE_LEVEL_LOW:
|
||
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
||
gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
|
||
| (2 << shift));
|
||
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
||
break;
|
||
|
||
case IRQ_TYPE_EDGE_RISING:
|
||
case IRQ_TYPE_LEVEL_HIGH:
|
||
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
||
gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
|
||
| (1 << shift));
|
||
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
||
break;
|
||
|
||
case IRQ_TYPE_EDGE_BOTH:
|
||
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
||
gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
|
||
raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
|
||
break;
|
||
|
||
default:
|
||
return -EINVAL;
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
static struct irq_chip mpc8xxx_irq_chip = {
|
||
.name = "mpc8xxx-gpio",
|
||
.irq_unmask = mpc8xxx_irq_unmask,
|
||
.irq_mask = mpc8xxx_irq_mask,
|
||
.irq_ack = mpc8xxx_irq_ack,
|
||
/* this might get overwritten in mpc8xxx_probe() */
|
||
.irq_set_type = mpc8xxx_irq_set_type,
|
||
};
|
||
|
||
static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
|
||
irq_hw_number_t hwirq)
|
||
{
|
||
irq_set_chip_data(irq, h->host_data);
|
||
irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
|
||
|
||
return 0;
|
||
}
|
||
|
||
static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
|
||
.map = mpc8xxx_gpio_irq_map,
|
||
.xlate = irq_domain_xlate_twocell,
|
||
};
|
||
|
||
struct mpc8xxx_gpio_devtype {
|
||
int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
|
||
int (*gpio_get)(struct gpio_chip *, unsigned int);
|
||
int (*irq_set_type)(struct irq_data *, unsigned int);
|
||
};
|
||
|
||
static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
|
||
.gpio_dir_out = mpc5121_gpio_dir_out,
|
||
.irq_set_type = mpc512x_irq_set_type,
|
||
};
|
||
|
||
static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
|
||
.gpio_dir_out = mpc5125_gpio_dir_out,
|
||
.irq_set_type = mpc512x_irq_set_type,
|
||
};
|
||
|
||
static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
|
||
.gpio_get = mpc8572_gpio_get,
|
||
};
|
||
|
||
static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
|
||
.irq_set_type = mpc8xxx_irq_set_type,
|
||
};
|
||
|
||
static const struct of_device_id mpc8xxx_gpio_ids[] = {
|
||
{ .compatible = "fsl,mpc8349-gpio", },
|
||
{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
|
||
{ .compatible = "fsl,mpc8610-gpio", },
|
||
{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
|
||
{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
|
||
{ .compatible = "fsl,pq3-gpio", },
|
||
{ .compatible = "fsl,ls1028a-gpio", },
|
||
{ .compatible = "fsl,ls1088a-gpio", },
|
||
{ .compatible = "fsl,qoriq-gpio", },
|
||
{}
|
||
};
|
||
|
||
static int mpc8xxx_probe(struct platform_device *pdev)
|
||
{
|
||
struct device_node *np = pdev->dev.of_node;
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc;
|
||
struct gpio_chip *gc;
|
||
const struct mpc8xxx_gpio_devtype *devtype = NULL;
|
||
struct fwnode_handle *fwnode;
|
||
int ret;
|
||
|
||
mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
|
||
if (!mpc8xxx_gc)
|
||
return -ENOMEM;
|
||
|
||
platform_set_drvdata(pdev, mpc8xxx_gc);
|
||
|
||
raw_spin_lock_init(&mpc8xxx_gc->lock);
|
||
|
||
mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
|
||
if (IS_ERR(mpc8xxx_gc->regs))
|
||
return PTR_ERR(mpc8xxx_gc->regs);
|
||
|
||
gc = &mpc8xxx_gc->gc;
|
||
gc->parent = &pdev->dev;
|
||
|
||
if (device_property_read_bool(&pdev->dev, "little-endian")) {
|
||
ret = bgpio_init(gc, &pdev->dev, 4,
|
||
mpc8xxx_gc->regs + GPIO_DAT,
|
||
NULL, NULL,
|
||
mpc8xxx_gc->regs + GPIO_DIR, NULL,
|
||
BGPIOF_BIG_ENDIAN);
|
||
if (ret)
|
||
return ret;
|
||
dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
|
||
} else {
|
||
ret = bgpio_init(gc, &pdev->dev, 4,
|
||
mpc8xxx_gc->regs + GPIO_DAT,
|
||
NULL, NULL,
|
||
mpc8xxx_gc->regs + GPIO_DIR, NULL,
|
||
BGPIOF_BIG_ENDIAN
|
||
| BGPIOF_BIG_ENDIAN_BYTE_ORDER);
|
||
if (ret)
|
||
return ret;
|
||
dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
|
||
}
|
||
|
||
mpc8xxx_gc->direction_output = gc->direction_output;
|
||
|
||
devtype = device_get_match_data(&pdev->dev);
|
||
if (!devtype)
|
||
devtype = &mpc8xxx_gpio_devtype_default;
|
||
|
||
/*
|
||
* It's assumed that only a single type of gpio controller is available
|
||
* on the current machine, so overwriting global data is fine.
|
||
*/
|
||
if (devtype->irq_set_type)
|
||
mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
|
||
|
||
if (devtype->gpio_dir_out)
|
||
gc->direction_output = devtype->gpio_dir_out;
|
||
if (devtype->gpio_get)
|
||
gc->get = devtype->gpio_get;
|
||
|
||
gc->to_irq = mpc8xxx_gpio_to_irq;
|
||
|
||
/*
|
||
* The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
|
||
* the input enable of each individual GPIO port. When an individual
|
||
* GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
|
||
* associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
|
||
* the port value to the GPIO Data Register.
|
||
*/
|
||
fwnode = dev_fwnode(&pdev->dev);
|
||
if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
|
||
of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
|
||
of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
|
||
is_acpi_node(fwnode))
|
||
gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
|
||
|
||
ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
|
||
if (ret) {
|
||
dev_err(&pdev->dev,
|
||
"GPIO chip registration failed with status %d\n", ret);
|
||
return ret;
|
||
}
|
||
|
||
mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
|
||
if (!mpc8xxx_gc->irqn)
|
||
return 0;
|
||
|
||
mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
|
||
MPC8XXX_GPIO_PINS,
|
||
&mpc8xxx_gpio_irq_ops,
|
||
mpc8xxx_gc);
|
||
|
||
if (!mpc8xxx_gc->irq)
|
||
return 0;
|
||
|
||
/* ack and mask all irqs */
|
||
gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
|
||
gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
|
||
|
||
ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
|
||
mpc8xxx_gpio_irq_cascade,
|
||
IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
|
||
mpc8xxx_gc);
|
||
if (ret) {
|
||
dev_err(&pdev->dev,
|
||
"failed to devm_request_irq(%d), ret = %d\n",
|
||
mpc8xxx_gc->irqn, ret);
|
||
goto err;
|
||
}
|
||
|
||
return 0;
|
||
err:
|
||
irq_domain_remove(mpc8xxx_gc->irq);
|
||
return ret;
|
||
}
|
||
|
||
static int mpc8xxx_remove(struct platform_device *pdev)
|
||
{
|
||
struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
|
||
|
||
if (mpc8xxx_gc->irq) {
|
||
irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
|
||
irq_domain_remove(mpc8xxx_gc->irq);
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
#ifdef CONFIG_ACPI
|
||
static const struct acpi_device_id gpio_acpi_ids[] = {
|
||
{"NXP0031",},
|
||
{ }
|
||
};
|
||
MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
|
||
#endif
|
||
|
||
static struct platform_driver mpc8xxx_plat_driver = {
|
||
.probe = mpc8xxx_probe,
|
||
.remove = mpc8xxx_remove,
|
||
.driver = {
|
||
.name = "gpio-mpc8xxx",
|
||
.of_match_table = mpc8xxx_gpio_ids,
|
||
.acpi_match_table = ACPI_PTR(gpio_acpi_ids),
|
||
},
|
||
};
|
||
|
||
static int __init mpc8xxx_init(void)
|
||
{
|
||
return platform_driver_register(&mpc8xxx_plat_driver);
|
||
}
|
||
|
||
arch_initcall(mpc8xxx_init);
|