2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
113 lines
3.0 KiB
C
113 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* DEC I/O ASIC interrupts.
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*
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* Copyright (c) 2002, 2003, 2013 Maciej W. Rozycki
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/types.h>
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#include <asm/dec/ioasic.h>
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#include <asm/dec/ioasic_addrs.h>
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#include <asm/dec/ioasic_ints.h>
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static int ioasic_irq_base;
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static void unmask_ioasic_irq(struct irq_data *d)
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{
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u32 simr;
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simr = ioasic_read(IO_REG_SIMR);
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simr |= (1 << (d->irq - ioasic_irq_base));
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ioasic_write(IO_REG_SIMR, simr);
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}
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static void mask_ioasic_irq(struct irq_data *d)
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{
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u32 simr;
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simr = ioasic_read(IO_REG_SIMR);
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simr &= ~(1 << (d->irq - ioasic_irq_base));
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ioasic_write(IO_REG_SIMR, simr);
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}
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static void ack_ioasic_irq(struct irq_data *d)
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{
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mask_ioasic_irq(d);
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fast_iob();
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}
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static struct irq_chip ioasic_irq_type = {
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.name = "IO-ASIC",
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.irq_ack = ack_ioasic_irq,
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.irq_mask = mask_ioasic_irq,
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.irq_mask_ack = ack_ioasic_irq,
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.irq_unmask = unmask_ioasic_irq,
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};
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static void clear_ioasic_dma_irq(struct irq_data *d)
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{
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u32 sir;
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sir = ~(1 << (d->irq - ioasic_irq_base));
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ioasic_write(IO_REG_SIR, sir);
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fast_iob();
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}
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static struct irq_chip ioasic_dma_irq_type = {
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.name = "IO-ASIC-DMA",
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.irq_ack = clear_ioasic_dma_irq,
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.irq_mask = mask_ioasic_irq,
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.irq_unmask = unmask_ioasic_irq,
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.irq_eoi = clear_ioasic_dma_irq,
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};
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/*
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* I/O ASIC implements two kinds of DMA interrupts, informational and
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* error interrupts.
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*
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* The formers do not stop DMA and should be cleared as soon as possible
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* so that if they retrigger before the handler has completed, usually as
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* a side effect of actions taken by the handler, then they are reissued.
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* These use the `handle_edge_irq' handler that clears the request right
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* away.
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*
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* The latters stop DMA and do not resume it until the interrupt has been
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* cleared. This cannot be done until after a corrective action has been
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* taken and this also means they will not retrigger. Therefore they use
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* the `handle_fasteoi_irq' handler that only clears the request on the
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* way out. Because MIPS processor interrupt inputs, one of which the I/O
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* ASIC is cascaded to, are level-triggered it is recommended that error
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* DMA interrupt action handlers are registered with the IRQF_ONESHOT flag
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* set so that they are run with the interrupt line masked.
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*
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* This mask has `1' bits in the positions of informational interrupts.
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*/
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#define IO_IRQ_DMA_INFO \
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(IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) | \
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IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) | \
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IO_IRQ_MASK(IO_INR_ISDN_TXDMA) | \
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IO_IRQ_MASK(IO_INR_ISDN_RXDMA) | \
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IO_IRQ_MASK(IO_INR_ASC_DMA))
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void __init init_ioasic_irqs(int base)
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{
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int i;
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/* Mask interrupts. */
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ioasic_write(IO_REG_SIMR, 0);
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fast_iob();
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for (i = base; i < base + IO_INR_DMA; i++)
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irq_set_chip_and_handler(i, &ioasic_irq_type,
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handle_level_irq);
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for (; i < base + IO_IRQ_LINES; i++)
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irq_set_chip_and_handler(i, &ioasic_dma_irq_type,
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1 << (i - base) & IO_IRQ_DMA_INFO ?
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handle_edge_irq : handle_fasteoi_irq);
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ioasic_irq_base = base;
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}
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