64fcc1fd32
The adau1701 has two power domains, DVDD and AVDD. Enable them both as long as the codec is in use. Signed-off-by: Pascal Huerst <pascal.huerst@gmail.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@kernel.org>
40 lines
1.3 KiB
Plaintext
40 lines
1.3 KiB
Plaintext
Analog Devices ADAU1701
|
|
|
|
Required properties:
|
|
|
|
- compatible: Should contain "adi,adau1701"
|
|
- reg: The i2c address. Value depends on the state of ADDR0
|
|
and ADDR1, as wired in hardware.
|
|
|
|
Optional properties:
|
|
|
|
- reset-gpio: A GPIO spec to define which pin is connected to the
|
|
chip's !RESET pin. If specified, the driver will
|
|
assert a hardware reset at probe time.
|
|
- adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs
|
|
the ADAU's PLL config pins are connected to.
|
|
The state of the pins are set according to the
|
|
configured clock divider on ASoC side before the
|
|
firmware is loaded.
|
|
- adi,pin-config: An array of 12 numerical values selecting one of the
|
|
pin configurations as described in the datasheet,
|
|
table 53. Note that the value of this property has
|
|
to be prefixed with '/bits/ 8'.
|
|
- avdd-supply: Power supply for AVDD, providing 3.3V
|
|
- dvdd-supply: Power supply for DVDD, providing 3.3V
|
|
|
|
Examples:
|
|
|
|
i2c_bus {
|
|
adau1701@34 {
|
|
compatible = "adi,adau1701";
|
|
reg = <0x34>;
|
|
reset-gpio = <&gpio 23 0>;
|
|
avdd-supply = <&vdd_3v3_reg>;
|
|
dvdd-supply = <&vdd_3v3_reg>;
|
|
adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>;
|
|
adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4
|
|
0x4 0x4 0x4 0x4 0x4 0x4>;
|
|
};
|
|
};
|