Commit Graph

79 Commits

Author SHA1 Message Date
Matt Carlson
8a6eac90e2 [TG3]: PCI command adjustment
This patch changes the way the driver works with the PCI command
register.  It adjusts the access size from dwords to words.  This patch
is done both as a PCI configuration space cleanup and as preparatory
work for PCI error recovery.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-22 02:59:51 -07:00
Matt Carlson
9c8a620e7f [TG3]: Add management FW version to ethtool report
This patch appends the management firmware version to the bootcode
firmware string reported through ethtool.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-22 02:59:50 -07:00
Matt Carlson
0527ba358a [TG3]: WOL defaults
This patch enables WOL by default if out-of-box WOL is enabled in the
NVRAM.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10 18:03:30 -07:00
Matt Carlson
9936bcf68a [TG3]: Add 5761 support
This patch adds rest of the miscellaneous code required to support the
5761.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10 18:03:07 -07:00
Matt Carlson
0d3031d9e6 [TG3]: Add 5761 APE support
This patch adds support for the new APE block, present in 5761 chips.
APE stands for Application Processing Engine.  The primary function of
the APE is to process manageability traffic, such as ASF.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10 18:02:43 -07:00
Matt Carlson
6b91fa0279 [TG3]: Add new 5761 NVRAM decode routines
This patch adds a new 5761-specific NVRAM strapping decode routine.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10 18:01:09 -07:00
Matt Carlson
d30cdd28fb [TG3]: Add 5784 and 5764 support.
This patch adds the support for 5784 and 5764 devices.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10 16:54:45 -07:00
Matt Carlson
795d01c523 [TG3]: ASIC decoding and basic CPMU support.
Newer products change the way the ASIC revision is obtained.  This patch
implements how the driver will extract the revision number.

This patch also adds preliminary CPMU support.  CPMU stands for Central
Power Management Unit.  The CPMU's role is to put the chip into lower
power states when the operating conditions allow it.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10 16:54:45 -07:00
Matt Carlson
9974a356b2 [TG3]: Walk PCI capability lists.
Newer tg3 devices shuffle around the registers in PCI configuration
space.  This patch changes the way the driver accesses the PCI
capabilities registers.  Hardcoded register locations are replaced with
offsets from pci_find_capability() return values.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10 16:54:44 -07:00
Stephen Hemminger
bea3348eef [NET]: Make NAPI polling independent of struct net_device objects.
Several devices have multiple independant RX queues per net
device, and some have a single interrupt doorbell for several
queues.

In either case, it's easier to support layouts like that if the
structure representing the poll is independant from the net
device itself.

The signature of the ->poll() call back goes from:

	int foo_poll(struct net_device *dev, int *budget)

to

	int foo_poll(struct napi_struct *napi, int budget)

The caller is returned the number of RX packets processed (or
the number of "NAPI credits" consumed if you want to get
abstract).  The callee no longer messes around bumping
dev->quota, *budget, etc. because that is all handled in the
caller upon return.

The napi_struct is to be embedded in the device driver private data
structures.

Furthermore, it is the driver's responsibility to disable all NAPI
instances in it's ->stop() device close handler.  Since the
napi_struct is privatized into the driver's private data structures,
only the driver knows how to get at all of the napi_struct instances
it may have per-device.

With lots of help and suggestions from Rusty Russell, Roland Dreier,
Michael Chan, Jeff Garzik, and Jamal Hadi Salim.

Bug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra,
Joseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan.

[ Ported to current tree and all drivers converted.  Integrated
  Stephen's follow-on kerneldoc additions, and restored poll_list
  handling to the old style to fix mutual exclusion issues.  -DaveM ]

Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-10 16:47:45 -07:00
Michael Chan
ee6a99b539 [TG3]: Fix msi issue with kexec/kdump.
Tina Yang <tina.yang@oracle.com> discovered an MSI related problem
when doing kdump.  The problem is that the kexec kernel is booted
without going through system reset, and as a result, MSI may already
be enabled when tg3_init_one() is called.  tg3_init_one() calls
pci_save_state() which will save the stale MSI state.  Later on in
tg3_open(), we call pci_enable_msi() to reconfigure MSI on the chip
before we reset the chip.  After chip reset, we call
pci_restore_state() which will put the stale MSI address/data back
onto the chip.

This is no longer a problem in the latest kernel because
pci_restore_state() has been changed to restore MSI state from
internal data structures which will guarantee restoring the proper
MSI state.

But I think we should still fix it.  Our save and restore sequence
can still cause very subtle problems down the road.  The fix is to
have our own functions save and restore precisely what we need.  We
also change it to save and restore state inside tg3_chip_reset() in a
more straight forward way.

Thanks to Tina for helping to test and debug the problem.

[ Bump driver version and release date. -DaveM ]

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-18 21:49:10 -07:00
Matt Carlson
70b65a2d62 [TG3]: Add missing NVRAM strapping.
This patch adds a missing NVRAM strapping for 5755 devices.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-11 19:48:50 -07:00
Matt Carlson
9ef8ca9974 [TG3]: Enable auto MDI.
This patch adds automatic MDI crossover support when autonegotiation is
turned off.  Automatic MDI crossover allows link to be established
without the use of a crossover cable.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-11 19:48:29 -07:00
Andrew Morton
2b3cb2e778 tg3: use flush_work_keventd()
Convert tg3 over to flush_work_keventd().  Remove nasty now-unneeded deadlock
avoidance logic.

(akpm: bypassed maintainers, sorry.  There are other patches which depend on
this)

Cc: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: David Howells <dhowells@redhat.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Michael Chan <mchan@broadcom.com>
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Oleg Nesterov <oleg@tv-sign.ru>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-09 12:30:51 -07:00
Matt Carlson
8ed5d97e5e [TG3]: Add ASPM workaround.
This patch adds workaround to fix performance problems caused by slow
PCIE L1->L0 transitions on ICH8 platforms.

Changed all magic numbers to constants as suggested by Jeff Garzik.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-07 00:25:49 -07:00
Michael Chan
7544b0972c [TG3]: Add TG3_FLAG_SUPPORT_MSI flag.
And fix up the code to always allow MSI on 5714 A2.

Call tg3_find_peer() earlier because we need that information before
we can determine whether we can set TG3_FLAG_SUPPORT_MSI or not.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-05 13:08:32 -07:00
Matt Carlson
98efd8a6be [TG3]: Eliminate the TG3_FLAG_5701_REG_WRITE_BUG flag.
This patch removes the use of the TG3_FLAG_5701_REG_WRITE_BUG flag.
It's logic is only used to set a function pointer and thus the
logic can be collapsed and the flag removed.

[ Comment tidy by Christoph Hellwig. -DaveM ]

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
2007-05-05 12:47:25 -07:00
Michael Chan
5cf64b8a73 [TG3]: Eliminate the TG3_FLAG_GOT_SERDES_FLOWCTL flag.
This flag does not do anything useful.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-05 12:11:21 -07:00
Gary Zambrano
a85feb8cfc [TG3]: WoL fixes.
Change TG3_FLAG_SERDES_WOL_CAP to TG3_FLAG_WOL_CAP to make it easier
to manage WoL.  This flag is now used consistently during ethtool WoL
setup and power setting changes.

Signed-off-by: Gary Zambrano <zambrano@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-05 11:52:19 -07:00
Michael Chan
d18edcb212 [TG3]: Exit irq handler during chip reset.
On most tg3 chips, the memory enable bit in the PCI command register
gets cleared during chip reset and must be restored before accessing
PCI registers using memory cycles.  The chip does not generate
interrupt during chip reset, but the irq handler can still be called
because of irq sharing or irqpoll.  Reading a register in the irq
handler can cause a master abort in this scenario and may result in a
crash on some architectures.

Use the TG3_FLAG_CHIP_RESETTING flag to tell the irq handler to exit
without touching any registers.  The checking of the flag is in the
"slow" path of the irq handler and will not affect normal performance.
The msi handler is not shared and therefore does not require checking
the flag.

Thanks to Bernhard Walle <bwalle@suse.de> for reporting the problem.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-03-25 18:48:08 -07:00
Michael Chan
1c46ae05d9 [TG3]: Eliminate the unused TG3_FLAG_SPLIT_MODE flag.
This flag to support multiple PCIX split completions was never used
because of hardware bugs.  This will make room for a new flag.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-03-25 18:48:06 -07:00
Michael Chan
7f62ad5d37 [TG3]: TSO workaround fixes.
1.  Add race condition check after netif_stop_queue().  tg3_tx() runs
    without netif_tx_lock and can race with tg3_start_xmit_dma_bug() ->
    tg3_tso_bug().

2.  Firmware TSO in 5703/5704/5705 also have the same TSO limitation,
    i.e. they cannot handle TSO headers bigger than 80 bytes.  Rename
    TG3_FL2_HW_TSO_1_BUG to TG3_FL2_TSO_BUG and set this flag on
    these chips as well.

3.  Update version to 3.74.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-26 11:42:47 -08:00
Michael Chan
569a5df859 [TG3]: Use constant for PHY register 0x1e.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-02-13 12:18:15 -08:00
Michael Chan
c1d2a1965a [TG3]: Add PHY workaround for 5755M.
Some PHY trim values need to be fine-tuned on 5755M to be
IEEE-compliant.

Update version to 3.72.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-01-09 00:30:06 -08:00
Michael Chan
60189ddff0 [TG3]: Power down/up 5906 PHY correctly.
The 5906 PHY requires a special register bit to power down and up the
PHY.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-12-17 21:59:22 -08:00
Michael Chan
9d26e21342 [TG3]: Add TG3_FLG2_IS_NIC flag.
Add Tg3_FLG2_IS_NIC flag to unambiguously determine whether the
device is NIC or onboard.  Previously, the EEPROM_WRITE_PROT flag was
overloaded to also mean onboard.  With the separation, we can
support some devices that are onboard but do not use eeprom write
protect.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-12-07 00:21:14 -08:00
Michael Chan
b16250e3d1 [TG3]: Add 5709 self-test support.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28 18:01:42 -07:00
Michael Chan
715116a126 [TG3]: Add 5709 PHY support.
Add support for the 5709 10/100 PHY.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28 18:01:41 -07:00
Michael Chan
b5d3772ccb [TG3]: Add basic 5906 support.
Add support for the new 5709 device.  This is a new 10/100 Mbps chip.
The mailbox access and firmware interface are quite different from
all other tg3 chips.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28 18:01:40 -07:00
Michael Chan
126a336822 [TG3]: Add 5722 and 5756 support.
Add IDs to support 5722 and 5756.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28 18:01:38 -07:00
Michael Chan
130b8e4d0e [TG3]: Improve ASF heartbeat.
Change to a different ASF heartbeat message code to improve
reliability.

There were some reports of unintended resets on real time kernels
where the timer may be slow and cause the heartbeat to be late.
Netpoll will also have the same problem because the timer irq will
be unavailable.

Using the new heartbeat code, the ASF firmware will also check the
ring condition before resetting the chip when the heartbeat is
expiring.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28 18:01:35 -07:00
Michael Chan
3d3ebe741b [TG3]: Improve 5704S autoneg.
Improve 5704S autoneg logic by using a serdes_counter field to keep
track of the transient states.  This eliminates a 200 msec busy
loop in the code.  Autoneg will take its course without the driver
busy waiting for it to finish.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-09-28 18:01:34 -07:00
Michael Chan
1b2a720506 [TG3]: Fix tx race condition
Fix a subtle race condition between tg3_start_xmit() and tg3_tx()
discovered by Herbert Xu <herbert@gondor.apana.org.au>:

CPU0					CPU1
tg3_start_xmit()
	if (tx_ring_full) {
		tx_lock
					tg3_tx()
						if (!netif_queue_stopped)
		netif_stop_queue()
		if (!tx_ring_full)
						update_tx_ring 
			netif_wake_queue()
		tx_unlock
	}

Even though tx_ring is updated before the if statement in tg3_tx() in
program order, it can be re-ordered by the CPU as shown above.  This
scenario can cause the tx queue to be stopped forever if tg3_tx() has
just freed up the entire tx_ring.  The possibility of this happening
should be very rare though.

The following changes are made:

1. Add memory barrier to fix the above race condition.

2. Eliminate the private tx_lock altogether and rely solely on
netif_tx_lock.  This eliminates one spinlock in tg3_start_xmit()
when the ring is full.

3. Because of 2, use netif_tx_lock in tg3_tx() before calling
netif_wake_queue().

4. Change TX_BUFFS_AVAIL to an inline function with a memory barrier.
Herbert and David suggested using the memory barrier instead of
volatile.

5. Check for the full wake queue condition before getting
netif_tx_lock in tg3_tx().  This reduces the number of unnecessary
spinlocks when the tx ring is full in a steady-state condition.

6. Update version to 3.65.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-08-07 21:46:02 -07:00
Michael Chan
52c0fd834e [TG3]: Add TSO workaround using GSO
Use GSO to workaround a rare TSO bug on some chips.  This hardware
bug may be triggered when the TSO header size is greater than 80
bytes.  When this condition is detected in a TSO packet, the driver
will use GSO to segment the packet to workaround the hardware bug.

Thanks to Juergen Kreileder <jk@blackdown.de> for reporting the
problem and collecting traces to help debug the problem.

And thanks to Herbert Xu <herbert@gondor.apana.org.au> for providing
the GSO mechanism that happens to be the perfect workaround for this
problem.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-30 14:11:57 -07:00
Michael Chan
1661394e78 [TG3]: Turn on hw fix for ASF problems
Clear a bit to enable a hardware fix for some ASF related problem.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-30 14:11:55 -07:00
Michael Chan
f92905deb9 [TG3]: Add rx BD workaround
Add workaround to limit the burst size of rx BDs being DMA'ed to the
chip.  This works around hardware errata on a number of 5750, 5752,
and 5755 chips.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-30 14:11:52 -07:00
Michael Chan
00b7050426 [TG3]: Convert to non-LLTX
Herbert Xu pointed out that it is unsafe to call netif_tx_disable()
from LLTX drivers because it uses dev->xmit_lock to synchronize
whereas LLTX drivers use private locks.

Convert tg3 to non-LLTX to fix this issue. tg3 is a lockless driver
where hard_start_xmit and tx completion handling can run concurrently
under normal conditions. A tx_lock is only needed to prevent
netif_stop_queue and netif_wake_queue race condtions when the queue
is full.

So whether we use LLTX or non-LLTX, it makes practically no
difference.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-17 21:58:45 -07:00
Michael Chan
df3e654818 [TG3]: Add recovery logic when MMIOs are re-ordered
Add recovery logic when we suspect that the system is re-ordering
MMIOs. Re-ordered MMIOs to the send mailbox can cause bogus tx
completions and hit BUG_ON() in the tx completion path.

tg3 already has logic to handle re-ordered MMIOs by flushing the MMIOs
that must be strictly ordered (such as the send mailbox).  Determining
when to enable the flush is currently a manual process of adding known
chipsets to a list.

The new code replaces the BUG_ON() in the tx completion path with the
call to tg3_tx_recover(). It will set the TG3_FLAG_MBOX_WRITE_REORDER
flag and reset the chip later in the workqueue to recover and start
flushing MMIOs to the mailbox.

A message to report the problem will be printed. We will then decide
whether or not to add the host bridge to the list of chipsets that do
re-ordering.

We may add some additional code later to print the host bridge's ID so
that the user can report it more easily.

The assumption that re-ordering can only happen on x86 systems is also
removed.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-17 21:26:26 -07:00
David S. Miller
f49639e643 [TG3]: Handle Sun onboard tg3 chips more correctly.
Get rid of all the SUN_570X logic and instead:

1) Make sure MEMARB_ENABLE is set when we probe the SRAM
   for config information.  If that is off we will get
   timeouts.

2) Always try to sync with the firmware, if there is no
   firmware running do not treat it as an error and instead
   just report it the first time we notice this condition.

3) If there is no valid SRAM signature, assume the device
   is onboard by setting TG3_FLAG_EEPROM_WRITE_PROT.

Update driver version and release date.

With help from Michael Chan and Fabio Massimo Di Nitto.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-06-09 12:03:51 -07:00
Michael Chan
c424cb249d [TG3]: Add phy workaround
Add some PHY workaround code to reduce jitter on some PHYs.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-04-29 18:56:34 -07:00
Michael Chan
bbadf503d7 [TG3]: Speed up SRAM access (2nd version)
Speed up SRAM read and write functions if possible by using MMIO
instead of config. cycles. With this change, the post reset signature
done at the end of D3 power change must now be moved before the D3
power change.

IBM reported a problem on powerpc blades during ethtool self test that
was caused by the memory test taking excessively long. Config.  cycles
are very slow on powerpc and the memory test can take more than 10
seconds to complete using config. cycles.

David Miller informed me that an earlier version of the patch caused
problems on sparc64 systems with built-in tg3 chips. This version
fixes the problem by excluding all SUN built-in tg3 chips from doing
MMIO SRAM access.

TG3_FLAG_EEPROM_WRITE_PROT is also set unconditionally when
TG3_FLG2_SUN_570X is set. This should be sane as all SUN chips are
built-in and do not require Vaux switching.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-04-09 22:25:46 -07:00
Michael Chan
d2d746f83b [TG3]: Kill some less useful flags
Kill the TG3_FLAG_NO_{TX|RX}_PSEUDO_CSUM flags because they are not
very useful. This will free up some bits for new flags.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-04-09 22:25:44 -07:00
Michael Chan
d3c7b88697 [TG3]: Add 5755 nvram support
Add 5755 nvram support.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-23 01:28:25 -08:00
Michael Chan
af36e6b6d7 [TG3]: Add 5755 support
Add support for new chip 5755 which is very similar to 5787.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-23 01:28:06 -08:00
Michael Chan
c4e6575c78 [TG3]: Add firmware version info
Add fw_version information to ethtool -i.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 22:29:32 -08:00
Michael Chan
fcfa0a32c7 [TG3]: Add new one-shot MSI handler
Support one-shot MSI on 5787.

This one-shot MSI idea is credited to David Miller. In this mode, MSI
disables itself automatically after it is generated, saving the driver
a register access to disable it for NAPI.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 22:28:41 -08:00
Michael Chan
5a6f3074c2 [TG3]: Add new hard_start_xmit
Support 5787 hardware TSO using a new flag TG3_FLG2_HW_TSO_2.

Since the TSO interface is slightly different and these chips have
finally fixed the 4GB DMA problem and do not have the 40-bit DMA
problem, a new hard_start_xmit is used for these chips. All previous
chips will use the old hard_start_xmit that is now renamed
tg3_start_xmit_dma_bug().

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 22:28:05 -08:00
Michael Chan
1b27777a9b [TG3]: Add 5787 nvram support
Support additional nvrams and new nvram format for 5787 and 5754.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 22:27:48 -08:00
Michael Chan
d9ab5ad12b [TG3]: Add 5787 and 5754 basic support
Add basic support for 2 new chips 5787 and 5754.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 22:27:35 -08:00
Michael Chan
4a29cc2e50 [TG3]: 40-bit DMA workaround part 2
The 40-bit DMA workaround recently implemented for 5714, 5715, and
5780 needs to be expanded because there may be other tg3 devices
behind the EPB Express to PCIX bridge in the 5780 class device.

For example, some 4-port card or mother board designs have 5704 behind
the 5714.

All devices behind the EPB require the 40-bit DMA workaround.

Thanks to Chris Elmquist again for reporting the problem and testing
the patch.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-19 13:21:12 -08:00