Commit Graph

69 Commits

Author SHA1 Message Date
Vipul Kumar Samar
d4f513ff12 Clk: SPEAr1340: Update sys clock parent array
sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl
register bit no. 23:25, with following possibilities

   0XX: pll1_clk
   10X: sys_synth_clk
   110: pll2_clk
   111: pll3_clk

Out of several possibilities (h/w wise) to select same clock parent for
sys_clk, current clock implementation was considering just one value.

When bootloader programmed different (valid) value to select a clock
parent then Linux breaks.

Here, we try to include all possibilities which can lead to same
clock selection thus making Linux independent of bootloader selection
values.

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2012-07-18 10:04:53 +05:30
Vipul Kumar Samar
d9ba8db215 clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.
This patch is to fix typing mistake of clk enable register of i2c1 and
uart1.

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2012-07-18 10:04:48 +05:30
Vipul Kumar Samar
a8f4bf0eb4 Clk:spear6xx:Fix: Rename clk ids within predefined limit
The max limit of con_id is 16 and dev_id is 20. As of now for spear6xx, many clk
ids are exceeding this predefined limit.

This patch is intended to rename clk ids like:
    mux_clk -> _mclk
    gate_clk -> _gclk
    synth_clk -> syn_clk
    ras_gen1_synth_gate_clk -> ras_syn1_gclk
    pll3_48m -> pll3_

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-07-18 10:04:42 +05:30
Vipul Kumar Samar
5cfc545f50 Clk:spear3xx:Fix: Rename clk ids within predefined limit
The max limit of con_id is 16 and dev_id is 20. As of now for spear3xx, many clk
ids are exceeding this predefined limit.

This patch is intended to rename clk ids like:
    mux_clk -> _mclk
    gate_clk -> _gclk
    synth_clk -> syn_clk
    ras_gen1_synth_gate_clk -> ras_syn1_gclk
    ras_pll3_48m -> ras_pll3_
    pll3_48m -> pll3_

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-07-18 10:04:39 +05:30
Vipul Kumar Samar
e28f1aa110 clk:spear1310:Fix: Rename clk ids within predefined limit
The max limit of con_id is 16 and dev_id is 20. As of now for spear1310, many
clk ids are exceeding this predefined limit.

This patch is intended to rename clk ids like:
    mux_clk -> _mclk
    gate_clk -> _gclk
    synth_clk -> syn_clk
    gmac_phy -> phy_
    gmii_125m_pad -> gmii_pad

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-07-18 10:04:36 +05:30
Vipul Kumar Samar
5cb6a9bcca clk:spear1340:Fix: Rename clk ids within predefined limit
The max limit of con_id is 16 and dev_id is 20. As of now for spear1340, many
clk ids are exceeding this predefined limit.

This patch rename clk ids like:
    mux_clk -> _mclk
    gate_clk -> _gclk
    synth_clk -> syn_clk
    gmac_phy -> phy_
    gmii_125m_pad_ -> gmii_pad

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-07-18 10:04:33 +05:30
Rajendra Nayak
863b13271f clk: fix parent validation in __clk_set_parent()
The below commit introduced a bug in __clk_set_parent()
which could cause it to *skip* the parent validation
which makes sure the parent passed to the api is a valid
one.

    commit 7975059db5
    Author: Rajendra Nayak <rnayak@ti.com>
    Date:   Wed Jun 6 14:41:31 2012 +0530

        clk: Allow late cache allocation for clk->parents

This was identified by the following compiler warning..

    drivers/clk/clk.c: In function '__clk_set_parent':
    drivers/clk/clk.c:1083:5: warning: 'i' may be used uninitialized in this function [-Wuninitialized]

.. as reported by Marc Kleine-Budde.

There were various options discussed on how to fix this, one
being initing 'i' to clk->num_parents, but the below approach
was found to be more appropriate as it also makes the 'parent
validation' code simpler to read.

Reported-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: stable@kernel.org
2012-07-03 12:05:14 -07:00
Marc Kleine-Budde
d03ac61daa clk: mxs: fix clock lookup after freeing init memory
The struct clk_lookup are marked as __initdata, resulting in being
removed from memory after the kernel finished booting. However this
leads to a NULL pointer de-ref if loading a module which uses clk_get.

This patch removes the __initdata from the struct clk_lookup.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-06-25 16:51:48 -07:00
Shawn Guo
d6dc55c185 clk: mxs: fix ref_io clock definition
The definition of clocks ref_io0 and ref_io1 were inverted.  It causes
a mmc regression on some boards right away.  Fix the regression by
correcting the ref_io clock definition.

Reported-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-06-25 16:51:48 -07:00
Pawel Moll
bf47b4fd8f clk: Check parent for NULL in clk_change_rate
clk_change_rate() is accessing parent's rate without checking
if the parent exists at all. In case of root clocks this will
cause NULL pointer dereference.

This patch follows what clk_calc_new_rates() does in such
situation.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: stable@kernel.org
2012-06-25 16:51:48 -07:00
Rajendra Nayak
7975059db5 clk: Allow late cache allocation for clk->parents
Parent clocks for muxes are cached in clk->parents to
avoid frequent lookups, however the cache allocation happens
only during clock registeration and later clk_set_parent()
assumes a cache space available and allocated.

This is not entirely true for platforms which do early clock
registerations wherein the cache allocation using kzalloc
could fail during clock registeration.

Allow cache allocation to happen later as part of clk_set_parent()
to help such cases and avoid crashes assuming a cache being
available.

While here also replace existing kmalloc() with kzalloc()
in the file.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: stable@kernel.org
2012-06-25 16:51:47 -07:00
Stefan Roese
3a35fc3a13 clk: SPEAr600: Fix ethernet clock name for DT based probing
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@st.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-06-25 16:51:47 -07:00
Viresh Kumar
10d8935f46 Viresh has moved
viresh.kumar@st.com email-id doesn't exist anymore as I have left the
company.  Replace ST's id with viresh.linux@gmail.com.

It also updates .mailmap file to fix address for 'git shortlog'

Signed-off-by: Viresh Kumar <viresh.linux@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-06-20 14:39:36 -07:00
Linus Torvalds
30b842889e arm-soc: soc specific changes, part 2
This adds support for the spear13xx platform, which has first been under
 review a long time ago and finally been completed after generic spear
 work has gone into the clock, dt and pinctrl branches.
 
 Also a number of updates for the samsung socs are part of this branch.
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Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc: soc specific changes (part 2) from Olof Johansson:
 "This adds support for the spear13xx platform, which has first been
  under review a long time ago and finally been completed after generic
  spear work has gone into the clock, dt and pinctrl branches.

  Also a number of updates for the samsung socs are part of this branch."

Fix up trivial conflicts in drivers/gpio/gpio-samsung.c that look much
worse than they are: the exonys5 init code was refactored in commit
fd454997d6 ("gpio: samsung: refactor gpiolib init for exynos4/5"), and
then commit f10590c983 ("ARM: EXYNOS: add GPC4 bank instance") added a
new gpio chip define and did tiny updates to the init code.

So the conflict diff looks like hell, but it's actually a fairly simple
change.

* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits)
  ARM: exynos: fix building with CONFIG_OF disabled
  ARM: EXYNOS: Add AUXDATA for i2c controllers
  ARM: dts: Update device tree source files for EXYNOS5250
  ARM: EXYNOS: Add device tree support for interrupt combiner
  ARM: EXYNOS: Add irq_domain support for interrupt combiner
  ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5
  ARM: EXYNOS: update irqs for EXYNOS5250 SoC
  ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
  ARM: EXYNOS: add GPC4 bank instance
  ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition
  ARM: EXYNOS: Modify the GIC physical address for static io-mapping
  ARM: EXYNOS: Add watchdog timer clock instance
  pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res
  SPEAr: Update MAINTAINERS and Documentation
  SPEAr13xx: Add defconfig
  SPEAr13xx: Add compilation support
  SPEAr13xx: Add dts and dtsi files
  pinctrl: Add SPEAr13xx pinctrl drivers
  pinctrl: SPEAr: Create macro for declaring GPIO PINS
  SPEAr13xx: Add common clock framework support
  ...
2012-05-26 13:05:55 -07:00
Linus Torvalds
84a442b9a1 arm-soc: device tree conversions, part 2
These continue the device tree work from part 1, this set is for the
 tegra, mxs and imx platforms, all of which have dependencies on clock
 or pinctrl changes submitted earlier.
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Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc device tree conversions (part 2) from Olof Johansson:
 "These continue the device tree work from part 1, this set is for the
  tegra, mxs and imx platforms, all of which have dependencies on clock
  or pinctrl changes submitted earlier."

Fix up trivial conflicts due to nearby changes in
drivers/{gpio/gpio,i2c/busses/i2c}-mxs.c

* tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (73 commits)
  ARM: dt: tegra: invert status=disable vs status=okay
  ARM: dt: tegra: consistent basic property ordering
  ARM: dt: tegra: sort nodes based on bus order
  ARM: dt: tegra: remove duplicate device_type property
  ARM: dt: tegra: consistenly use lower-case for hex constants
  ARM: dt: tegra: format regs properties consistently
  ARM: dt: tegra: gpio comment cleanup
  ARM: dt: tegra: remove unnecessary unit addresses
  ARM: dt: tegra: whitespace cleanup
  ARM: dt: tegra cardhu: fix typo in SDHCI node name
  ARM: dt: tegra: cardhu: register core regulator tps62361
  ARM: dt: tegra30.dtsi: Add SMMU node
  ARM: dt: tegra20.dtsi: Add GART node
  ARM: dt: tegra30.dtsi: Add Memory Controller(MC) nodes
  ARM: dt: tegra20.dtsi: Add Memory Controller(MC) nodes
  ARM: dt: tegra: Add device tree support for AHB
  ARM: dts: enable audio support for imx28-evk
  ARM: dts: enable i2c device for imx28-evk
  i2c: mxs: add device tree probe support
  ARM: dts: enable mmc for imx28-evk
  ...
2012-05-26 12:57:47 -07:00
Arnd Bergmann
3c0dec5f58 Merge branch 'clk-next' of git://git.linaro.org/people/mturquette/linux into next/clock
* 'clk-next' of git://git.linaro.org/people/mturquette/linux:
  clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate().
  clk: Provide dummy clk_unregister()
  ARM: Kirkwood: Replace clock gating
  ARM: Orion: Audio: Add clk/clkdev support
  ARM: Orion: PCIE: Add support for clk
  ARM: Orion: XOR: Add support for clk
  ARM: Orion: CESA: Add support for clk
  ARM: Orion: SDIO: Add support for clk.
  ARM: Orion: NAND: Add support for clk, if there is one.
  ARM: Orion: EHCI: Add support for enabling clocks
  ARM: Orion: SATA: Add per channel clk/clkdev support.
  ARM: Orion: UART: Get the clock rate via clk_get_rate().
  ARM: Orion: WDT: Add clk/clkdev support
  ARM: Orion: Eth: Add clk/clkdev support.
  ARM: Orion: SPI: Add clk/clkdev support.
  ARM: Orion: Add clocks using the generic clk infrastructure.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-05-16 16:35:25 +02:00
Saravana Kannan
7e0fa1b5fa clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate().
The clk_set_rate() code shouldn't check the clock's enable count when
validating CLK_SET_RATE_GATE flag since the enable count could change after
the validation. Similar to clk_set_parent(), it should instead check the
prepare count. The prepare count should go to zero only when the end user
expects the clock to not be enabled in the future. Since the code already
grabs the prepare count before validation, it's not possible for prepare
count to change after validation and by association not possible for a well
behaving end user to enable the clock while the set rate is in progress.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Reviewed-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-15 22:42:10 -07:00
Mark Brown
1df5c939f6 clk: Provide dummy clk_unregister()
While there's no actual implementation behind it having the call to use
in drivers makes them feel neater from a driver author point of view. An
actual implementation can wait for someone who needs to use the function
in a real system.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
[mturquette@linaro.org: void return type instead of int -EINVAL]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-15 12:02:39 -07:00
Viresh Kumar
0b928af1f4 SPEAr13xx: Add common clock framework support
This patch adds SPEAr1310 and SPEAr1340's clock framework support. It is based
on earlier support for SPEAr3xx family.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@ti.com>
2012-05-14 17:34:05 +02:00
Shawn Guo
ef9b4d3996 mmc: mxs-mmc: get rid of the use of cpu_is_xxx
The register HW_SSP_VERSION is broken for ssp version detection,
as the address of the register is different between imx23 and imx28.
Let's use platform_device_id to detect the device, so that the use
of cpu_is_xxx can be removed.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Chris Ball <cjb@laptop.org>
2012-05-13 08:05:31 +08:00
Arnd Bergmann
eae0185a96 Merge branch 'spear/clock' into next/clock
Viresh Kumar <viresh.kumar@st.com> writes:

 This is rebased over a (merge of Mike's/clk-next & SPEAr's DT) + Russell's
 patch: CLKDEV: provide helpers for common clock framework rebased over them.

* spear/clock:
  SPEAr: Switch to common clock framework
  SPEAr: Call clk_prepare() before calling clk_enable
  SPEAr: clk: Add General Purpose Timer Synthesizer clock
  SPEAr: clk: Add Fractional Synthesizer clock
  SPEAr: clk: Add Auxiliary Synthesizer clock
  SPEAr: clk: Add VCO-PLL Synthesizer clock

Conflicts:
	drivers/clk/Makefile

[Arnd: rebased again without the spear/dt branch]

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-05-13 00:11:06 +02:00
Viresh Kumar
5df33a62c4 SPEAr: Switch to common clock framework
SPEAr SoCs used its own clock framework since now. From now on they will move to
use common clock framework.

This patch updates existing SPEAr machine support to adapt for common clock
framework.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-05-12 21:44:12 +02:00
Viresh Kumar
a45896bd3a SPEAr: clk: Add General Purpose Timer Synthesizer clock
All SPEAr SoC's contain GPT Synthesizers. Their Fout is derived from
following equations:

Fout= Fin/((2 ^ (N+1)) * (M+1))

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
2012-05-12 21:19:27 +02:00
Viresh Kumar
270b9f421e SPEAr: clk: Add Fractional Synthesizer clock
All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from
following equations:

Fout = Fin / (2 * div) (division factor)
div is 17 bits:-
     0-13 (fractional part)
     14-16 (integer part)
     div is (16-14 bits).(13-0 bits) (in binary)

     Fout = Fin/(2 * div)
     Fout = ((Fin / 10000)/(2 * div)) * 10000
     Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
     Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000

div << 14 is simply 17 bit value written at register.

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
2012-05-12 21:19:27 +02:00
Viresh Kumar
5335a639ec SPEAr: clk: Add Auxiliary Synthesizer clock
All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on
values of eq, x and y.

Fout from synthesizer can be given from two equations:
Fout1 = (Fin * X/Y)/2		EQ1
Fout2 = Fin * X/Y		EQ2

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
2012-05-12 21:19:26 +02:00
Viresh Kumar
55b8fd4f42 SPEAr: clk: Add VCO-PLL Synthesizer clock
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations

- In normal mode
  vco = (2 * M[15:8] * Fin)/N

- In Dithered mode
  vco = (2 * M[15:0] * Fin)/(256 * N)

pll_rate = vco/2^p

vco and pll are very closely bound to each other,
"vco needs to program: mode, m & n" and "pll needs to program p",
both share common enable/disable logic and registers.

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
2012-05-12 21:19:23 +02:00
Shawn Guo
8c92013643 dma: mxs-dma: make platform_device_id more generic
Rewrite mxs_dma_is_apbh and mxs_dma_is_apbx in order to support
other SoCs like imx6q and reform the platform_device_id for the
better further dt support.

Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Huang Shijie <b32955@freescale.com>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Vinod Koul <vinod.koul@intel.com>
2012-05-12 13:32:17 +08:00
Shawn Guo
2954ff395b ARM: mxs: add initial device tree support for imx23-evk board
It adds initial device tree support for imx23-evk board, and only
serial console is enabled.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
2012-05-12 13:32:17 +08:00
Dong Aisheng
bc3a59c1b7 ARM: mxs: add initial device tree support for imx28-evk board
This patch includes basic dt support which can boot via nfs rootfs.

Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
2012-05-12 13:32:16 +08:00
Arnd Bergmann
93c6d8927f Merge branch 'clk/mxs' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/clock
Shawn Guo <shawn.guo@linaro.org> writes:

  mxs common clk porting for v3.5.  It depends on the following two branches.

  [1] git://git.linaro.org/people/mturquette/linux.git clk-next
  [2] http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-arm.git clkdev

  As the mxs device tree conversion will constantly touch clock files,
  to save the conflicts, the updated mxs/dt branch coming later will
  based on this pull-request.

* 'clk/mxs' of git://git.linaro.org/people/shawnguo/linux-2.6:
  ARM: mxs: remove now unused timer_clk argument from mxs_timer_init
  ARM: mxs: remove old clock support
  ARM: mxs: switch to common clk framework
  ARM: mxs: change the lookup name for fec phy clock
  ARM: mxs: request clock for timer
  clk: mxs: add clock support for imx28
  clk: mxs: add clock support for imx23
  clk: mxs: add mxs specific clocks

Includes an update to Linux 3.4-rc6

Conflicts:
	drivers/clk/Makefile

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-05-11 17:15:31 +02:00
Arnd Bergmann
e12ff34402 Merge branch 'depends/rmk/clkdev' into next/clock
* depends/rmk/clkdev:
  CLKDEV: provide helpers for common clock framework
  ARM: 7392/1: CLKDEV: Optimize clk_find()
  ARM: 7376/1: clkdev: Implement managed clk_get()
2012-05-11 17:13:00 +02:00
Sascha Hauer
f0948f59db clk: add a fixed factor clock
Having fixed factors/dividers in hardware is a common pattern, so
add a basic clock type doing this. It basically describes a fixed
factor clock using a nominator and a denominator.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
[mturquette@linaro.org: constify parent_names in static init macro]
[mturquette@linaro.org: copy/paste bug from mux in static init macro]
[mturquette@linaro.org: fix error handling in clk_register_fixed_factor]
[mturquette@linaro.org: improve division accuracy; thanks to Saravana]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-08 14:13:25 -07:00
Mike Turquette
31df9db995 clk: mux: assign init data
The original conversion to struct clk_hw_init failed to add the pointer
assignment in clk_register_mux.

Signed-off-by: Mike Turquette <mturquette@linaro.org>
Reported-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-05-08 14:13:07 -07:00
Mike Turquette
d269b974e3 clk: remove COMMON_CLK_DISABLE_UNUSED
Exposing this option generates confusion and incorrect behavior for
single-image builds across platforms.  Enable this behavior permanently.

Signed-off-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Saravana Kannan <skannan@codeaurora.org>
2012-05-08 14:12:42 -07:00
Mike Turquette
63f5c3b2b1 clk: prevent spurious parent rate propagation
Patch 'clk: always pass parent_rate into .round_rate' made a subtle
change to the semantics of .round_rate.  It is now expected for the
parent's rate to always be passed in, simplifying the implemenation of
various .round_rate callback definitions.

However the patch also introduced a bug in clk_calc_new_rates whereby a
clock without the CLK_SET_RATE_PARENT flag set could still propagate a
rate change up to a parent clock if the the .round_rate callback
modified the &best_parent_rate value in any way.

This patch fixes the issue at the framework level (in
clk_calc_new_rates) by specifically handling the case where the
CLK_SET_RATE_PARENT flag is not set.

Signed-off-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
2012-05-08 14:11:53 -07:00
Shawn Guo
50260924af ARM: mxs: remove now unused timer_clk argument from mxs_timer_init
With old mxs clock support removed, the timer_clk argument of
mxs_timer_init is unused now, so remove it.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-09 00:02:43 +08:00
Shawn Guo
2664681fa4 ARM: mxs: switch to common clk framework
It switches mxs clock support to common clk framework based drivers.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-09 00:02:41 +08:00
Shawn Guo
7d81397cd9 clk: mxs: add clock support for imx28
Add imx28 clock support based on common clk framework.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-09 00:02:38 +08:00
Shawn Guo
ff261b7f64 clk: mxs: add clock support for imx23
Add imx23 clock support based on common clk framework.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-09 00:02:36 +08:00
Shawn Guo
23b5e15a29 clk: mxs: add mxs specific clocks
Add mxs specific clocks, pll, reference clock (PFD), integer divider
and fractional divider.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-05-09 00:02:35 +08:00
Russell King
e9d7f40654 CLKDEV: provide helpers for common clock framework
The common clock framework allocates clocks dynamically.  Provide a
set of helpers to streamline the clkdev registration of the clock
lookups to avoid repetitive code sequences.

Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2012-05-02 09:30:32 +01:00
Viresh Kumar
0e1c030175 clk: clk_set_rate() must fail if CLK_SET_RATE_GATE is set and clk is enabled
This is well documented but isn't implemented. clk_set_rate() must check if
flags have CLK_SET_RATE_GATE bit set and is enabled too.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-01 18:13:38 -07:00
Saravana Kannan
0197b3ea0f clk: Use a separate struct for holding init data.
Create a struct clk_init_data to hold all data that needs to be passed from
the platfrom specific driver to the common clock framework during clock
registration. Add a pointer to this struct inside clk_hw.

This has several advantages:
* Completely hides struct clk from many clock platform drivers and static
  clock initialization code that don't care for static initialization of
  the struct clks.
* For platforms that want to do complete static initialization, it removed
  the need to directly mess with the struct clk's fields while still
  allowing to statically allocate struct clk. This keeps the code more
  future proof even if they include clk-private.h.
* Simplifies the generic clk_register() function and allows adding optional
  fields in the future without modifying the function signature.
* Simplifies the static initialization of clocks on all platforms by
  removing the need for forward delcarations or convoluted macros.

Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[mturquette@linaro.org: kept DEFINE_CLK_* macros and __clk_init]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergman <arnd.bergmann@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Jamie Iles <jamie@jamieiles.com>
Cc: Richard Zhao <richard.zhao@linaro.org>
Cc: Saravana Kannan <skannan@codeaurora.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Deepak Saxena <dsaxena@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
2012-05-01 18:13:20 -07:00
Rob Herring
01033be174 clk: select CLKDEV_LOOKUP for COMMON_CLK
Using the common clock infrastructure without the common clkdev code makes
little sense, so select CLKDEV_LOOKUP for COMMON_CLK.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-04-24 16:37:41 -07:00
Viresh Kumar
1b2f99037a clk: Don't set clk->new_rate twice
if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) is true, then
we don't need to set clk->new_rate here, as we will call clk_calc_subtree()
afterwards and it also sets clk->new_rate.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-04-24 16:37:41 -07:00
Viresh Kumar
fbc42aab54 clk: clk-gate: Create clk_gate_endisable()
This patch tries to remove duplicate code for clk_gate clocks. This creates
another routine clk_gate_endisable() which will take care of enable/disable
clock with knowledge of CLK_GATE_SET_TO_DISABLE flag.

It works on following logic:

For enabling clock, enable = 1
	set2dis = 1	-> clear bit	-> set = 0
	set2dis = 0	-> set bit	-> set = 1

For disabling clock, enable = 0
	set2dis = 1	-> set bit	-> set = 1
	set2dis = 0	-> clear bit	-> set = 0

So, result is always: enable xor set2dis.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-04-24 16:37:40 -07:00
Shawn Guo
f4d8af2e5a clk: propagate round_rate for CLK_SET_RATE_PARENT case
Need to propagate round_rate call for the clk that has no .round_rate
operation but with flag CLK_SET_RATE_PARENT set.

For example, clk_mux is a clk with no .round_rate operation.  However,
it could likely be in a clk_set_rate propagation path, saying it has
parent clk who has .round_rate and .set_rate operations.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-04-24 16:37:40 -07:00
Shawn Guo
1c0035d710 clk: pass parent_rate into .set_rate
For most of .set_rate implementation, parent_rate will be used, so just
like passing parent_rate into .recalc_rate, let's pass parent_rate into
.set_rate too.

It also updates the kernel doc for .set_rate ops.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-04-24 16:37:40 -07:00
Shawn Guo
81536e072b clk: always pass parent_rate into .round_rate
The parent_rate will likely be used by most .round_rate implementation
no matter whether flag CLK_SET_RATE_PARENT is set or not, so let's
always pass parent_rate into .round_rate.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-04-24 16:37:39 -07:00
Mike Turquette
27d545915f clk: basic: improve parent_names & return errors
This patch is the basic clk version of 'clk: core: copy parent_names &
return error codes'.

The registration functions are changed to allow the core code to copy
the array of strings and allow platforms to declare those arrays as
__initdata.

This patch also converts all of the basic clk registration functions to
return error codes which better aligns them with the existing clk.h api.

Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-04-24 16:37:39 -07:00