Some HW blocks have errata which requires specific slave idle mode
under certain conditions.
This patch adds an hwmod API to allow setting slave idlemode
ensuring that any SYSCONFIG register updates go through hwmod.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
First, this patch adds new worst-case latency values to the
omap_device_pm_latency struct. Here the worst-case measured latencies
for the activate and deactivate hooks are stored.
In addition, add an option to auto-adjust the latency values used for
device activate/deactivate.
By setting a new 'OMAP_DEVICE_LATENCY_AUTO_ADJUST' flag in the
omap_device_pm_latency struct, the omap_device layer automatically
adjusts the activate/deactivate latencies to the worst-case measured
values.
Anytime a new worst-case value is found, it is printed to the console.
Here is an example log during boot using UART2 s an example. After
boot, the OPP is manually changed to the 125MHz OPP:
[...]
Freeing init memory: 128K
omap_device: serial8250.2: new worst case deactivate latency 0: 30517
omap_device: serial8250.2: new worst case activate latency 0: 30517
omap_device: serial8250.2: new worst case activate latency 0: 218139648
omap_device: serial8250.2: new worst case deactivate latency 0: 61035
omap_device: serial8250.2: new worst case activate latency 0: 278076171
omap_device: serial8250.2: new worst case activate latency 0: 298614501
omap_device: serial8250.2: new worst case activate latency 0: 327331542
/ # echo 125000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
omap_device: serial8250.2: new worst case deactivate latency 0: 91552
Motivation: this can be used as a technique to automatically determine
the worst case latency values. The current method of printing a
warning on every violation is too noisy to actually interact the
console in order to set low OPP to discover latencies.
Another motivation for this patch is that the activate/deactivate
latenices can vary depending on the idlemode of the device. While
working on the UARTs, I noticed that when using no-idle, the activate
latencies were as high as several hundred msecs as shown above. When
the UARTs are in smart-idle, the max latency is well under 100 usecs.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This patch only affects documentation; no functional changes are
included.
Clean up comments in the current clockdomain, powerdomain code and
header files. This mostly involves conversion to kerneldoc format,
although some clarifications are also included.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This patch rearranges the order of structure members in struct powerdomain
to avoid wasting memory due to alignment restrictions.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add usecounting for wakeup and sleep dependencies. In the current
situation, if several functions add dependencies on the same
clockdomains, when the first dependency removal function is called,
the dependency will be incorrectly removed from the hardware.
Add clkdm_clear_all_wkdeps() and clkdm_clear_all_sleepdeps(), which
provide a fast and usecounting-consistent way to clear all hardware
clockdomain dependencies, since accesses to these registers can be
quite slow. pm{2,3}4xx.c has been updated to use these new functions.
The original version of this patch did not touch these files, which
previously wrote directly to the wkdep registers, and thus confused
the usecounting code. This problem was found by Kevin Hilman
<khilman@deeprootsystems.com>.
N.B.: This patch introduces one significant functional difference over
the previous pm34xx.c code: sleepdeps are now cleared during
clockdomain initialization, whereas previously they were left
untouched. This has been tested by Kevin and confirmed to work.
The original version of this patch also did not take into
consideration that some clockdomains do not have sleep or wakeup
dependency sources, which caused NULL pointer dereferences. This
problem was debugged and fixed by Kevin Hilman
<khilman@deeprootsystems.com>.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jouni Högander <jouni.hogander@nokia.com>
OMAP clockdomains and powerdomains are currently defined statically,
only registered at boot, and never unregistered, so we can remove the
unregister function and the locking. A variant of this was originally
suggested a while ago by Dmitry Baryshkov <dbaryshkov@gmail.com>.
This version of this patch contains an additional fix from Kevin Hilman
<khilman@deeprootsystems.com> to address one of the pwrdm_for_each_nolock()
users in mach-omap2/pm-debug.c. Thanks Kevin.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Dmitry Baryshkov <dbaryshkov@gmail.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Move clockdomain wakeup dependency and sleep dependency data
structures from the powerdomain layer to the clockdomain layer, where
they belong. These dependencies were originally placed in the
powerdomain layer due to unclear documentation; however, it is clear
now that these dependencies are between clockdomains. For OMAP2/3,
this is not such a big problem, but for OMAP4 this needs to be fixed.
Thanks to Benoît Cousson <b-cousson@ti.com> for his advice on this
patch.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
One of the OMAP1 clocks can use the fixed divisor recalculation code
introduced in the OMAP2 clock code, so rename the
omap2_fixed_divisor_recalc() function to omap_fixed_divisor_recalc()
and make it available to all OMAPs. A followup patch converts the OMAP1
clock.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add CK_* flags for the two new Sitara chips, AM3505 and AM3517, and
the OMAP34xx die shrink, OMAP36xx/OMAP37xx. Introduce a new CK_*
flag, CK_3XXX, that marks all clocks that are common to OMAP3 family
chips. CK_343X now refers to clocks that are available only on
OMAP34{1,2,3,4}0 (WTBU) and OMAP35{03,15,25,30} (any version).
At some point, the RATE_IN_* flags should be updated also.
While here, add some documentation describing the chip families
covered by these clock flags.
This patch is partially based on patches from Ranjith Lohithakshan
<ranjithl@ti.com> and Vishwanath Sripathy <vishwanath.bs@ti.com>.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Ranjith Lohithakshan <ranjithl@ti.com>
Cc: Vishwanath Sripathy <vishwanath.bs@ti.com>
AM3517/05 has a few additional control module registers defined mainly
to control the new IP's. This patch adds support for those new registers.
Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Here the ".clkstctrl_reg" field is added to the clockdomain stucture
as the module offsets for OMAP4 do not map one to one for powerdomains
and clockdomains as it used to for OMAP3. Hence we need to use absolute
addresses to access the control registers. Some of the clock domains have
modules falling in the address space of PRM partition. Hence necessitating
the use of absolute adresses.
Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Taking care of the platform specific and common power domains with
proper checks. Also refining some Macros according to the latest
OMAP4 requirements.
Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
The Autogenerated OMAP4 power domain specific file (mach-omap2/powerdomains44xx.h)
is added here.
This file is auto-generated using python scripting and following is the list of the people
involved:
Paul Walmsley
Benoit Cousson
Abhijit Pagare
Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Some of the OMAP4 specific chip level initialisations are taken care of.
Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
[paul@pwsan.com: updated to use '4430ES1' rather than simply '4430'; updated
to apply after the intervening cpu.h/id.c patch; thanks also to Tony
for catching a bug in my rewrite]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
OMAP GP timers keep running for a few cycles after they are stopped,
which can cause the timer to expire and generate an interrupt. The
pending interrupt will prevent e.g. OMAP from entering suspend, thus
we ack it manually. Only applicable on OMAP2/3/4.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
During suspend, the kernel timekeeping subsystem is shut down. Before
suspend and upon resume, it uses a weak function
read_persistent_clock() to determine the amount of time that elapsed
during suspend.
This function was not implemented on OMAP, so from the timekeeping
subsystem perspective (and thus userspace as well) it appeared that no
time elapsed during suspend.
This patch uses the 32k sync timer as a the persistent clock.
NOTE: This does *NOT* fully handle wrapping of the 32k sync timer, so
more than one wrapping of the 32k sync timer during suspend may
cause problems. Also note there are not interrupts when the 32k
sync timer wraps, so something else has to be done.
Reported-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
OMAP interrupt controller goes to unknown state when there is right
combination of l3,l4 sleep/wake-up transitions, l4 autoidle in
interrupt controller and some interrupt. When this happens, interrupts
are not delivered to ARM anymore and ARM will remain in WFI (wait for
interrupt) until interrupt controller is forced to wake-up
(i.e. lauterbach).
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Suspending drivers may still generate interrupts just before their suspend is
completed. Any pending interrupts here will prevent sleep.
Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
We need to set the omap_chip.oc carefully for the clocks to work.
To fix this, set the omap_chip.oc in omap3_check_features() based
on the CONTROL_IDCODE and silicon revision registers.
Also add handling for 34xx es3.1.2 as es3.1 for now.
Fixes booting on at least overo board.
Based on an earlier patch by Paul Walmsley <paul@pwsan.com>.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
In the current implementation the sysconfig value is read into
_sysc_cache once and an actual update to the sysconfig register
happens only if the new value paased is differnt from the one in _sysc_cache.
_sysc_cache is updated only if _HWMOD_SYSCONFIG_LOADED is not set.
This can lead to the follwing issue if off mode is enabled in modules
which employs "always-retore" mechanism of context save and restore.
a. The module sets the sysconfig register through omap_device_enable.
Here _sysc_cache is updated with the value written to the sysconfig
register and left.
b. The power domain containig the module enters off mode and the
module context is lost.
c. The module in use becomes active and calls omap_device_enable to
enable itself. Here a read of sysconfig register does not happen
as _HWMOD_SYSCONFIG_LOADED flag is set. The value to be written
to the sysconfig register will be same as the one written in step a.
Since _sysc_cache reflects the previous written value an update
of the sysconfig register does not happen.
This means in modules which employs "always-restore" mechanism
after off , the sysconfig regsiters will never get updated.
This patch introduces a flag SYSC_NO_CACHE which if set ensures that the
sysconfig register is always read into _sysc_cache before an update is
attempted.
This flags need to be set only by modules which does not do a context save
but re-initializes the registers every time the module is accessed. This
includes modules like i2c, smartreflex etc.
Signed-off-by: Thara Gopinath <thara@ti.com>
[paul@pwsan.com: tweaked to apply on a different head, added flag comment]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
A subsequent patch adds code on OMAP2xxx to dynamically allocate the
CPUFreq frequency table in clk_init_cpufreq_table(), so for it to
avoid a leak, it will need a corresponding function to free the
memory. This patch adds clk_exit_cpufreq_table() with generic
code to call a chip-specific variant inside the clockfw_lock spinlock via
struct clk_functions.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The only symbols that should be exported are symbols that are to be
called from loadable kernel modules, e.g., device drivers. In the
context of plat-omap/clock.c, these should only be the Linux clock
interface symbols as defined by include/linux/clk.h. Core code
doesn't need these symbols to be exported. Also, clean up an old
comment while here.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Commit 10db25fea4 causes the following
kernel messages during N800 boot (and presumably all other 2420
boards):
[ 0.000000] BUG: mapping for 0x58000000 at 0xe0000000 overlaps vmalloc space
[ 0.000000] BUG: mapping for 0x59000000 at 0xe1000000 overlaps vmalloc space
[ 0.000000] BUG: mapping for 0x5a000000 at 0xe2000000 overlaps vmalloc space
Fix by remapping the IVA memory areas somewhere outside vmalloc space.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Out of the three major OMAP2 chip types, OMAP2420, OMAP2430, and OMAP3430,
we only map the IVA on OMAP2420. The memory mapping is not shared between
OMAP2420 and OMAP2430, so it is inappropriate to label those macros as
'24XX'; this patch changes them to '2420'.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Commit 9905a43b made struct backlight_ops const. Omap was
setting check_fb dynamically, which caused the following
compile error:
drivers/video/backlight/omap1_bl.c: In function 'omapbl_probe':
drivers/video/backlight/omap1_bl.c:142: error: assignment of read-only variable 'omapbl_ops'
Turns out pdata->check_fb is not being used, so just remove
it to fix the compile.
Cc: Emese Revfy <re.emese@gmail.com>
Cc: Richard Purdie <rpurdie@linux.intel.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit 35c9049b27 added
drivers/spi/omap_spi_100k.c.
This patch add the related clocks and pin muxing
entries to make the driver work on omap7xx platforms.
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
In its current form, the omap_mcbsp_request() function can return after
irq_request() failure without any cleanups, effectively locking out the port
forever with clocks left running. Fix it.
Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Acked-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds support for phoenix interrupt framework. New iInterrupt
status register A, B, C are introduced in Phoenix and are cleared on write.
Due to the differences in interrupt handling with respect to TWL4030,
twl6030-irq.c is created for TWL6030 PMIC
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
In original implementation, the revision passed to
these macros contained revision number in lower nibble.
But, later the revision bits (OMAP_REVBITS_XX) were
defined to use omap_revision[15:08] where revision
number is containied in higher nibble.
This patch updates the macros; else incorrect revision
is detected for OMAP35xx devices.
Signed-off-by: Sanjeev Premi <premi@ti.com>
The runtime detection of OMAP3515 and OMAP3525
was reversed.
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Remove unused data type omap_gpio_switch_config
Thereby also get rid of following sparse warnings:
arch/arm/plat-omap/include/plat/board.h :121:20:
warning: dubious bitfield without explicit `signed' or `unsigned'
arch/arm/plat-omap/include/plat/board.h :122:19:
warning: dubious bitfield without explicit `signed' or `unsigned'
arch/arm/plat-omap/include/plat/board.h :123:24:
warning: dubious bitfield without explicit `signed' or `unsigned'
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
Acked-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Comment in omap_init_devices asks to keep init calls and their
implementations in alphabetical order, so let it be that way.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
For NAND devices '2' should be used with GPMC_CONFIG1_DEVICETYPE
instead of '1'.
Signed-off-by: Vimal Singh <vimalsingh@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch adds new function: omap_serial_init_port(port) that can be
used to initialize only selected UARTs as serial ports. Platforms can
then in their board files call this function instead of omap_serial_init()
if they don't want to use all UARTs as serial ports.
Signed-off-by: Mika Westerberg <ext-mika.1.westerberg@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The AuxCoreBoot0 and AuxCoreBoot1 can be only accessed in secure
mode. Replace the current code with secure monitor API's to access/modify
these registers.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch fixes the public sram base address and available
size on OMAP4430.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch fixes the OMAP4430 cpu detection. The IC rev detection is
done with hawkeye and rev. Note that rev does not map directly to
defined processor revision numbers as ES1.0 uses value 0.It also fixes
the SCM base address to read the correct ID_CODE register.
Also the cpu_is_omap44xx() and cpu_is_omap443x() correctly populated
instead of always being true
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This change adds MUX pin configuration and clocks for I2C support
to OMAP 730 and 850-based devices.
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This change implements USB client side support into the HTC
Herald board configuration. It uses a similar, but updated
algorithm to initialize the USB as is used in the linwizard
project.
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
All of the LCD DMA code in plat-omap/dma.c appears to be OMAP1-only (and
apparently only is available on a subset of OMAP1 chips).
Move this code to mach-omap1/lcd_dma.c.
Tested on OMAP1510 Amstrad Delta.
Compile-tested with omap_generic_2420_defconfig.
Reported-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Use smc91x_platdata to setup smc91x, so we can get rid of OMAP specific stuff
in smc91x driver
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
