Until we synchronize against device removal this limits the damage of
use after free bugs to the driver's own objects. Unless we implement
reference counting we need to ensure at least a subset of a remote
device is valid at all times. We follow the lead of other libsas
drivers that also preallocate devices.
This also enforces maximum remote device accounting at the lldd layer,
but the core may still run out of RNC's before we hit this limit.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Replace the device completion infrastructure with the controller wide
event queue. There was a potential for the stop and ready notifications
to corrupt each other, now that cannot happen.
The stop pending flag cannot be used until devices are statically
allocated. We temporarily need to maintain a completion to handle
waiting for an object that has disappeared, but we can at least stop
scribbling on freed memory.
A future change will also get rid of the "stopping" state as it should
not be exposed to the rest of the driver.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
isci_host_by_id() should have been a clue that an array would have been
a simpler approach.
Reported-by: James Bottomley <James.Bottomley@suse.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Prepare the timer api for the arrival of dynamic creation and
destruction events from the core. It pretended to do this previously
but the core to date only used it in a static init-time only fashion.
This is an interim fix until a cleaner event queue can be developed.
1/ make all locking external to the api (add WARN_ONCE to verify)
2/ add a timer_destroy interface (to be used by the core)
3/ use del_timer_sync() prior to deallocating timer data
4/ delete the "timer_list" indirection, we only have timers allocated
for the isci_host
5/ fix detection of timer list allocation errors
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Undo the open coded and incorrect translation of the oem parameter sas
address to its libsas expected format.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Removed all callbacks in the deprecated.c. Core will call the appropriate
functions directly.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
The lldd actively disallows requests in the "starting" state. Retrying
or holding off commands in this state is sub-optimal:
1/ it adds another state check to the fast path
2/ retrying can cause libsas to give up
However, isci's ->lldd_dev_found() routine already waits for controller
start to complete before allowing further progress. Checking the
"starting" state in isci_task_execute_task and the isr is redundant and
misleading. Clean this up and introduce a controller-wide event queue
to start reeling in "completion" proliferation in the driver.
The "stopping" state cleanups are in a similar vein, rely on the the isr
and other paths being precluded from occurring rather than implementing
state checking logic.
Reported-by: Christoph Hellwig <hch@infradead.org>
Cc: Jeff Garzik <jeff@garzik.org>
Signed-off-by: Edmund Nadolski <edmund.nadolski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
The indirection is unecessary and broken in the current case that assigns the
handlers based on a not up-to-date pdev->msix_enabled value.
Route the handlers directly to the requisite core routines.
Todo: hook up error interrupt handling
Reported-by: Jeff Garzik <jeff@garzik.org>
Cc: Christoph Hellwig <hch@infradead.org>
Signed-off-by: Edmund Nadolski <edmund.nadolski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Support for the up to 2x4-port 6Gb/s SAS controllers embedded in the
chipset.
This is a snapshot of the first publicly available version of the driver,
commit 4c1db2d0 in the 'historical' branch.
git://git.kernel.org/pub/scm/linux/kernel/git/djbw/isci.git historical
Signed-off-by: Maciej Trela <maciej.trela@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Edmund Nadolski <edmund.nadolski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
