Commit Graph

7 Commits

Author SHA1 Message Date
William Breathitt Gray
aaf96e51de gpio: pci-idio-16: Fix port memory offset for get_multiple callback
The ioread8 function expects a memory offset argument. This patch fixes
the ports array to provide the memory addresses of the respective device
I/O registers.

Fixes: 810ebfc5ef ("gpio: pci-idio-16: Implement get_multiple callback")
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-04-27 00:55:16 +02:00
William Breathitt Gray
810ebfc5ef gpio: pci-idio-16: Implement get_multiple callback
The ACCES I/O PCI-IDIO-16 series of devices provides 16
optically-isolated digital inputs accessed via two 8-bit ports. Since
eight input lines are acquired on a single port input read, the
PCI-IDIO-16 GPIO driver may improve multiple input reads by utilizing a
get_multiple callback. This patch implements the
idio_16_gpio_get_multiple function which serves as the respective
get_multiple callback.

Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-26 10:24:06 +02:00
Thierry Reding
f0fbe7bce7 gpio: Move irqdomain into struct gpio_irq_chip
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08 14:06:21 +01:00
Julia Cartwright
ea38ce081d gpio: pci-idio-16: make use of raw_spinlock variants
The pci-idio-16 gpio driver currently implements an irq_chip for handling
interrupts; due to how irq_chip handling is done, it's necessary for the
irq_chip methods to be invoked from hardirq context, even on a a
real-time kernel.  Because the spinlock_t type becomes a "sleeping"
spinlock w/ RT kernels, it is not suitable to be used with irq_chips.

A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.

Signed-off-by: Julia Cartwright <julia@ni.com>
Acked-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-03-28 11:13:59 +02:00
William Breathitt Gray
deab2b0524 gpio: pci-idio-16: Fix PCI BAR index
The PCI BAR0 and BAR1 for the PCI-IDIO-16 hold information for the PLX
9052 bridge chip on the device. The PCI BAR2 holds the necessary base
address for I/O control of the PCI-IDIO-16. This patch corrects the PCI
BAR index mismatch for the PCI-IDIO-16 GPIO driver.

Fixes: 02e74fc040 ("gpio: Add GPIO support for the ACCES PCI-IDIO-16")
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-02-13 16:19:10 +01:00
William Breathitt Gray
fd254a23ca gpio: pci-idio-16: Fix PCI device ID code
The ACCES PCI-IDIO-16 has a PCI device ID code of 0x0DC8. It is
incorrect to use the PCI device ID code of the ACCES PCI-IIRO-8
(0x0F00). This patch fixes the said PCI device ID code mismatch.

Fixes: 02e74fc040 ("gpio: Add GPIO support for the ACCES PCI-IDIO-16")
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-02-13 15:46:13 +01:00
William Breathitt Gray
02e74fc040 gpio: Add GPIO support for the ACCES PCI-IDIO-16
The ACCES PCI-IDIO-16 device provides 32 lines of digital I/O (16 lines
of optically-isolated digital inputs for AC and DC control signals, and
16 lines of solid state switch digital outputs). An interrupt is
generated when any of the inputs change state (low to high or high to
low). Input filter control is not supported by this driver, and input
filters are deactivated by this driver.

Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-02-06 11:01:06 +01:00