of the churn behind us. Significant stuff in this pull includes:
- A set of new Chinese translations
- Italian translation updates
- A mechanism from Mauro to automatically format Documentation/features
for the built docs
- Automatic cross references without explicit :ref: markup
- A new reset-controller document
- An extensive new document on reporting problems from Thorsten
That last patch also adds the CC-BY-4.0 license to LICENSES/dual; there was
some discussion on this, but we seem to have consensus and an ack from Greg
for that addition.
-----BEGIN PGP SIGNATURE-----
iQFDBAABCAAtFiEEIw+MvkEiF49krdp9F0NaE2wMflgFAl/XyewPHGNvcmJldEBs
d24ubmV0AAoJEBdDWhNsDH5YUeYH/AiNNlVIF/80T45TAkm+1kpy2Fb+d/5wbtGK
PB7OTXPyDmmqwZNldlF9IsRhp5W+wYC3PNlulYMG44hT7/Jqf2CMFw8SOZqGLmBV
LhWwoS+TAWLB19IOOMrVXbhAlNsX01NwBDY/dwONjW1Jcu+tuAsBR47T9lKjw4kJ
qGFGMQTvZG9Ig1x7E6X38mAd7W3SD1viNuUePS2YcoB15GAocWfVVHvu1r+RHUTS
27ET8tWzMMuiaCAD6toVY9L4T7iCI7YSPXQm8BOkf/f4LXDnpo8Fo11LE5ozTAh3
+avnNt8vnrRXc06MnzwsvNHm2TqN97B4shkeDiPAV3ySXI8Zu/w=
=HScX
-----END PGP SIGNATURE-----
Merge tag 'docs-5.11' of git://git.lwn.net/linux
Pull documentation updates from Jonathan Corbet:
"A much quieter cycle for documentation (happily), with, one hopes, the
bulk of the churn behind us. Significant stuff in this pull includes:
- A set of new Chinese translations
- Italian translation updates
- A mechanism from Mauro to automatically format
Documentation/features for the built docs
- Automatic cross references without explicit :ref: markup
- A new reset-controller document
- An extensive new document on reporting problems from Thorsten
That last patch also adds the CC-BY-4.0 license to LICENSES/dual;
there was some discussion on this, but we seem to have consensus and
an ack from Greg for that addition"
* tag 'docs-5.11' of git://git.lwn.net/linux: (50 commits)
docs: fix broken cross reference in translations/zh_CN
docs: Note that sphinx 1.7 will be required soon
docs: update requirements to install six module
docs: reporting-issues: move 'outdated, need help' note to proper place
docs: Update documentation to reflect what TAINT_CPU_OUT_OF_SPEC means
docs: add a reset controller chapter to the driver API docs
docs: make reporting-bugs.rst obsolete
docs: Add a new text describing how to report bugs
LICENSES: Add the CC-BY-4.0 license
Documentation: fix multiple typos found in the admin-guide subdirectory
Documentation: fix typos found in admin-guide subdirectory
kernel-doc: Fix example in Nested structs/unions
docs: clean up sysctl/kernel: titles, version
docs: trace: fix event state structure name
docs: nios2: add missing ReST file
scripts: get_feat.pl: reduce table width for all features output
scripts: get_feat.pl: change the group by order
scripts: get_feat.pl: make complete table more coincise
scripts: kernel-doc: fix parsing function-like typedefs
Documentation: fix typos found in process, dev-tools, and doc-guide subdirectories
...
fast_second_level_miss handler for the TLBTEMP area has an assumption
that page table directory entry for the TLBTEMP address range is 0. For
it to be true the TLBTEMP area must be aligned to 4MB boundary and not
share its 4MB region with anything that may use a page table. This is
not true currently: TLBTEMP shares space with vmalloc space which
results in the following kinds of runtime errors when
fast_second_level_miss loads page table directory entry for the vmalloc
space instead of fixing up the TLBTEMP area:
Unable to handle kernel paging request at virtual address c7ff0e00
pc = d0009275, ra = 90009478
Oops: sig: 9 [#1] PREEMPT
CPU: 1 PID: 61 Comm: kworker/u9:2 Not tainted 5.10.0-rc3-next-20201110-00007-g1fe4962fa983-dirty #58
Workqueue: xprtiod xs_stream_data_receive_workfn
a00: 90009478 d11e1dc0 c7ff0e00 00000020 c7ff0000 00000001 7f8b8107 00000000
a08: 900c5992 d11e1d90 d0cc88b8 5506e97c 00000000 5506e97c d06c8074 d11e1d90
pc: d0009275, ps: 00060310, depc: 00000014, excvaddr: c7ff0e00
lbeg: d0009275, lend: d0009287 lcount: 00000003, sar: 00000010
Call Trace:
xs_stream_data_receive_workfn+0x43c/0x770
process_one_work+0x1a1/0x324
worker_thread+0x1cc/0x3c0
kthread+0x10d/0x124
ret_from_kernel_thread+0xc/0x18
Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Now that several arch documents were converted to ReST,
add their indexes to Documentation/index.rst and remove the
:orphan: from them.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Rename the xtensa documentation files to ReST, add an
index for them and adjust in order to produce a nice html
output via the Sphinx build system.
At its new index.rst, let's add a :orphan: while this is not linked to
the main index.rst file, in order to avoid build warnings.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Add booting.txt to Documentation/xtensa with description of boot
parameters representation and passing to the kernel.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Cover kernel addresses above 0x90000000 by the shadow map. Enable
HAVE_ARCH_KASAN when MMU is enabled. Provide kasan_early_init that fills
shadow map with writable copies of kasan_zero_page. Call
kasan_early_init right after mmu initialization in the setup_arch.
Provide kasan_init that allocates proper shadow map pages from the
memblock and puts these pages into the shadow map for addresses from
VMALLOC area to the end of KSEG. Call kasan_init right after memblock
initialization. Don't use KASAN for the boot code, MMU and KASAN
initialization and page fault handler. Make kernel stack size 4 times
larger when KASAN is enabled to avoid stack overflows.
GCC 7.3, 8 or newer is required to build the xtensa kernel with KASAN.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
The virtual address space between the page table and the VMALLOC region
is big enough to host KASAN shadow map and there's enough space between
the VMALLOC area and KSEG for the fixmap and kmap.
Move fixmap and kmap to the gap between VMALLOC area and KSEG, just
above the KSEG. Reorder entries in the kernel memory layout printing
code. Drop duplicate PGTABLE_START definition, use
XCHAL_PAGE_TABLE_VADDR instead.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
The Devicetree Specification has superseded the ePAPR as the
base specification for bindings. Update files in Documentation
to reference the new document.
First reference to ePAPR in Documentation/devicetree/bindings/arm/cci.txt
is generic, remove it.
Some files are not updated because there is no hypervisor chapter
in the Devicetree Specification:
Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
Documenation/virtual/kvm/api.txt
Documenation/virtual/kvm/ppc-pv.txt
Signed-off-by: Frank Rowand <frank.rowand@sony.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Make kernel load address explicit, independent of the selected MMU
configuration and configurable from Kconfig. Do not restrict it to the
first 512MB of the physical address space.
Cleanup kernel memory layout macros:
- rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR;
- drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS;
- introduce PHYS_OFFSET and use it in __va and __pa definitions;
- synchronize MMU/noMMU vectors, drop unused NMI vector;
- replace hardcoded vectors offset of 0x3000 with Kconfig symbol.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
MMUv3 is able to support low memory bigger than 128MB.
Implement 256MB and 512MB KSEG layouts:
- add Kconfig selector for KSEG layout;
- add KSEG base address, size and alignment definitions to
arch/xtensa/include/asm/kmem_layout.h;
- use new definitions in TLB initialization;
- add build time memory map consistency checks.
See Documentation/xtensa/mmu.txt for the details of new memory layouts.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Use the simple-bus node to discover the io area, and remap the cached and
bypass io ranges. The parent-bus-address value of the first triplet in the
"ranges" property is used. This value is rounded down to the nearest 256MB
boundary. The length of the io area is fixed at 256MB; the "ranges" property
length value is ignored.
Other limitations: (1) only the first simple-bus node is considered, and (2)
only the first triplet of the "ranges" property is considered.
See ePAPR 1.1 §6.5 for the simple-bus node description, and §2.3.8 for the
"ranges" property description.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Make the WT entry match table 4-52 of the Xtensa ISA RM (RD-2012.5).
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
In order to use S32C1I instruction on cores with ATOMCTL SR the register
must be properly initialized.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
