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dt-bindings: riscv: correct e51 and u54-mc CPU bindings

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All existing boards with sifive,e51 and sifive,u54-mc use it on top of
sifive,rocket0 compatible:

  arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed:
    ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long
    Additional items are not allowed ('riscv' was unexpected)
    Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected)
    'riscv' was expected

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210920132559.151678-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2021-09-20 15:25:59 +02:00 committed by Rob Herring
parent 6f4276ecc0
commit f46428f066
1 changed files with 6 additions and 2 deletions
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8
Documentation/devicetree/bindings/riscv/cpus.yaml
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@ -31,9 +31,7 @@ properties:
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e51
- sifive,e71
- sifive,u54-mc
- sifive,u74-mc
- sifive,u54
- sifive,u74
@ -41,6 +39,12 @@ properties:
- sifive,u7
- canaan,k210
- const: riscv
- items:
- enum:
- sifive,e51
- sifive,u54-mc
- const: sifive,rocket0
- const: riscv
- const: riscv # Simulator only
description:
Identifies that the hart uses the RISC-V instruction set