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dt-bindings: clock: u8500: Rewrite in YAML and extend

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This rewrites the ux500/u8500 clock bindings in YAML schema and extends them
with the PRCC reset controller.

The bindings are a bit idiomatic but it just reflects their age, the ux500
platform was used as guinea pig for early device tree conversion of platforms
in 2015. The new subnode for the reset controller follows the pattern of the
old bindings and adds a node with reset-cells for this.

Cc: devicetree@vger.kernel.org
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210921184803.1757916-1-linus.walleij@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Linus Walleij 2021-09-21 20:48:02 +02:00 committed by Stephen Boyd
parent 6880fa6c56
commit f2b883bbdd
3 changed files with 172 additions and 64 deletions
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121
Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ST-Ericsson DB8500 (U8500) clocks
maintainers:
- Ulf Hansson <ulf.hansson@linaro.org>
- Linus Walleij <linus.walleij@linaro.org>
description: While named "U8500 clocks" these clocks are inside the
DB8500 digital baseband system-on-chip and its siblings such as
DB8520. These bindings consider the clocks present in the SoC
itself, not off-chip clocks. There are four different on-chip
clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
control management unit) clocks and PRCC (peripheral reset and
clock controller) clocks. For some reason PRCC 4 does not exist so
the itemization can be a bit unintuitive.
properties:
compatible:
enum:
- stericsson,u8500-clks
- stericsson,u8540-clks
- stericsson,u9540-clks
reg:
items:
- description: PRCC 1 register area
- description: PRCC 2 register area
- description: PRCC 3 register area
- description: PRCC 5 register area
- description: PRCC 6 register area
prcmu-clock:
description: A subnode with one clock cell for PRCMU (power, reset, control
management unit) clocks. The cell indicates which PRCMU clock in the
prcmu-clock node the consumer wants to use.
type: object
properties:
'#clock-cells':
const: 1
additionalProperties: false
prcc-periph-clock:
description: A subnode with two clock cells for PRCC (peripheral
reset and clock controller) peripheral clocks. The first cell indicates
which PRCC block the consumer wants to use, possible values are 1, 2, 3,
5, 6. The second cell indicates which clock inside the PRCC block it
wants, possible values are 0 thru 31.
type: object
properties:
'#clock-cells':
const: 2
additionalProperties: false
prcc-kernel-clock:
description: A subnode with two clock cells for PRCC (peripheral reset
and clock controller) kernel clocks. The first cell indicates which PRCC
block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The
second cell indicates which clock inside the PRCC block it wants, possible
values are 0 thru 31.
type: object
properties:
'#clock-cells':
const: 2
additionalProperties: false
prcc-reset-controller:
description: A subnode with two reset cells for the reset portions of the
PRCC (peripheral reset and clock controller). The first cell indicates
which PRCC block the consumer wants to use, possible values are 1, 2, 3
5 and 6. The second cell indicates which reset line inside the PRCC block
it wants to control, possible values are 0 thru 31.
type: object
properties:
'#reset-cells':
const: 2
additionalProperties: false
rtc32k-clock:
description: A subnode with zero clock cells for the 32kHz RTC clock.
type: object
properties:
'#clock-cells':
const: 0
additionalProperties: false
smp-twd-clock:
description: A subnode for the ARM SMP Timer Watchdog cluster with zero
clock cells.
type: object
properties:
'#clock-cells':
const: 0
additionalProperties: false
required:
- compatible
- reg
- prcmu-clock
- prcc-periph-clock
- prcc-kernel-clock
- rtc32k-clock
- smp-twd-clock
additionalProperties: false

64
Documentation/devicetree/bindings/clock/ux500.txt
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Clock bindings for ST-Ericsson Ux500 clocks
Required properties :
- compatible : shall contain only one of the following:
"stericsson,u8500-clks"
"stericsson,u8540-clks"
"stericsson,u9540-clks"
- reg : shall contain base register location and length for
CLKRST1, 2, 3, 5, and 6 in an array. Note the absence of
CLKRST4, which does not exist.
Required subnodes:
- prcmu-clock: a subnode with one clock cell for PRCMU (power,
reset, control unit) clocks. The cell indicates which PRCMU
clock in the prcmu-clock node the consumer wants to use.
- prcc-periph-clock: a subnode with two clock cells for
PRCC (programmable reset- and clock controller) peripheral clocks.
The first cell indicates which PRCC block the consumer
wants to use, possible values are 1, 2, 3, 5, 6. The second
cell indicates which clock inside the PRCC block it wants,
possible values are 0 thru 31.
- prcc-kernel-clock: a subnode with two clock cells for
PRCC (programmable reset- and clock controller) kernel clocks
The first cell indicates which PRCC block the consumer
wants to use, possible values are 1, 2, 3, 5, 6. The second
cell indicates which clock inside the PRCC block it wants,
possible values are 0 thru 31.
- rtc32k-clock: a subnode with zero clock cells for the 32kHz
RTC clock.
- smp-twd-clock: a subnode for the ARM SMP Timer Watchdog cluster
with zero clock cells.
Example:
clocks {
compatible = "stericsson,u8500-clks";
/*
* Registers for the CLKRST block on peripheral
* groups 1, 2, 3, 5, 6,
*/
reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
<0x8000f000 0x1000>, <0xa03ff000 0x1000>,
<0xa03cf000 0x1000>;
prcmu_clk: prcmu-clock {
#clock-cells = <1>;
};
prcc_pclk: prcc-periph-clock {
#clock-cells = <2>;
};
prcc_kclk: prcc-kernel-clock {
#clock-cells = <2>;
};
rtc_clk: rtc32k-clock {
#clock-cells = <0>;
};
smp_twd_clk: smp-twd-clock {
#clock-cells = <0>;
};
};

51
include/dt-bindings/reset/stericsson,db8500-prcc-reset.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _DT_BINDINGS_STE_PRCC_RESET
#define _DT_BINDINGS_STE_PRCC_RESET
#define DB8500_PRCC_1 1
#define DB8500_PRCC_2 2
#define DB8500_PRCC_3 3
#define DB8500_PRCC_6 6
/* Reset lines on PRCC 1 */
#define DB8500_PRCC_1_RESET_UART0 0
#define DB8500_PRCC_1_RESET_UART1 1
#define DB8500_PRCC_1_RESET_I2C1 2
#define DB8500_PRCC_1_RESET_MSP0 3
#define DB8500_PRCC_1_RESET_MSP1 4
#define DB8500_PRCC_1_RESET_SDI0 5
#define DB8500_PRCC_1_RESET_I2C2 6
#define DB8500_PRCC_1_RESET_SPI3 7
#define DB8500_PRCC_1_RESET_SLIMBUS0 8
#define DB8500_PRCC_1_RESET_I2C4 9
#define DB8500_PRCC_1_RESET_MSP3 10
#define DB8500_PRCC_1_RESET_PER_MSP3 11
#define DB8500_PRCC_1_RESET_PER_MSP1 12
#define DB8500_PRCC_1_RESET_PER_MSP0 13
#define DB8500_PRCC_1_RESET_PER_SLIMBUS 14
/* Reset lines on PRCC 2 */
#define DB8500_PRCC_2_RESET_I2C3 0
#define DB8500_PRCC_2_RESET_PWL 1
#define DB8500_PRCC_2_RESET_SDI4 2
#define DB8500_PRCC_2_RESET_MSP2 3
#define DB8500_PRCC_2_RESET_SDI1 4
#define DB8500_PRCC_2_RESET_SDI3 5
#define DB8500_PRCC_2_RESET_HSIRX 6
#define DB8500_PRCC_2_RESET_HSITX 7
#define DB8500_PRCC_1_RESET_PER_MSP2 8
/* Reset lines on PRCC 3 */
#define DB8500_PRCC_3_RESET_SSP0 1
#define DB8500_PRCC_3_RESET_SSP1 2
#define DB8500_PRCC_3_RESET_I2C0 3
#define DB8500_PRCC_3_RESET_SDI2 4
#define DB8500_PRCC_3_RESET_SKE 5
#define DB8500_PRCC_3_RESET_UART2 6
#define DB8500_PRCC_3_RESET_SDI5 7
/* Reset lines on PRCC 6 */
#define DB8500_PRCC_3_RESET_RNG 0
#endif