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RISC-V: Skip setting up PMPs on traps

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The RISC-V ISA manual says that PMPs are WARL, but it appears the K210
doesn't implement them and instead traps on the unsupported accesses.
This patch handles those traps by just skipping the PMP
initialization entirely, under the theory that machines that trap on PMP
accesses must allow memory accesses as otherwise they're pretty useless.

Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Palmer Dabbelt 2020-04-07 11:33:40 -07:00
parent 045c654220
commit eb077c9c38
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1 changed files with 10 additions and 1 deletions
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11
arch/riscv/kernel/head.S
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@ -161,11 +161,20 @@ ENTRY(_start_kernel)
/* Reset all registers except ra, a0, a1 */
call reset_regs
/* Setup a PMP to permit access to all of memory. */
/*
* Setup a PMP to permit access to all of memory. Some machines may
* not implement PMPs, so we set up a quick trap handler to just skip
* touching the PMPs on any trap.
*/
la a0, pmp_done
csrw CSR_TVEC, a0
li a0, -1
csrw CSR_PMPADDR0, a0
li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X)
csrw CSR_PMPCFG0, a0
.align 2
pmp_done:
/*
* The hartid in a0 is expected later on, and we have no firmware