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docs: core-api: add cachetlb documentation

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The cachetlb.txt is already in ReST format. So, move it to the
core-api guide, where it belongs.

Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
This commit is contained in:
Mauro Carvalho Chehab 2018-05-07 06:35:41 -03:00 committed by Jonathan Corbet
parent fe8703cc0d
commit de0f51e4b1
5 changed files with 3 additions and 4 deletions
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2
Documentation/00-INDEX
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@ -76,8 +76,6 @@ bus-devices/
- directory with info on TI GPMC (General Purpose Memory Controller) - directory with info on TI GPMC (General Purpose Memory Controller)
bus-virt-phys-mapping.txt bus-virt-phys-mapping.txt
- how to access I/O mapped memory from within device drivers. - how to access I/O mapped memory from within device drivers.
cachetlb.txt
- describes the cache/TLB flushing interfaces Linux uses.
cdrom/ cdrom/
- directory with information on the CD-ROM drivers that Linux has. - directory with information on the CD-ROM drivers that Linux has.
cgroup-v1/ cgroup-v1/

0
Documentation/cachetlb.txt → Documentation/core-api/cachetlb.rst
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1
Documentation/core-api/index.rst
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@ -14,6 +14,7 @@ Core utilities
kernel-api kernel-api
assoc_array assoc_array
atomic_ops atomic_ops
cachetlb
refcount-vs-atomic refcount-vs-atomic
cpu_hotplug cpu_hotplug
idr idr

2
Documentation/memory-barriers.txt
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@ -2903,7 +2903,7 @@ is discarded from the CPU's cache and reloaded. To deal with this, the
appropriate part of the kernel must invalidate the overlapping bits of the appropriate part of the kernel must invalidate the overlapping bits of the
cache on each CPU. cache on each CPU.
See Documentation/cachetlb.txt for more information on cache management. See Documentation/core-api/cachetlb.rst for more information on cache management.
CACHE COHERENCY VS MMIO CACHE COHERENCY VS MMIO

2
Documentation/translations/ko_KR/memory-barriers.txt
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@ -2846,7 +2846,7 @@ CPU 의 캐시에서 RAM 으로 쓰여지는 더티 캐시 라인에 의해 덮
문제를 해결하기 위해선, 커널의 적절한 부분에서 각 CPU 의 캐시 안의 문제가 되는 문제를 해결하기 위해선, 커널의 적절한 부분에서 각 CPU 의 캐시 안의 문제가 되는
비트들을 무효화 시켜야 합니다. 비트들을 무효화 시켜야 합니다.
캐시 관리에 대한 더 많은 정보를 위해선 Documentation/cachetlb.txt 를 캐시 관리에 대한 더 많은 정보를 위해선 Documentation/core-api/cachetlb.rst 를
참고하세요. 참고하세요.