drm/i915/psr: Implement PSR2 w/a for gen9
Found this while browsing Bspec. Looks like it applies to both skl and
kbl.
v2: Also for bxt (Art).
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Sonika Jindal <sonika.jindal@intel.com>
Cc: Durgadoss R <durgadoss.r@intel.com>
Cc: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Cc: "Runyan, Arthur J" <arthur.j.runyan@intel.com>
Reviewed-by: Sonika Jindal<sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463642060-30728-1-git-send-email-daniel.vetter@ffwll.ch
(cherry picked from commit dc00b6a07c
)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
This commit is contained in:
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@ -6031,6 +6031,7 @@ enum skl_disp_power_wells {
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#define CHICKEN_PAR1_1 _MMIO(0x42080)
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#define DPA_MASK_VBLANK_SRD (1 << 15)
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#define FORCE_ARB_IDLE_PLANES (1 << 14)
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#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
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#define _CHICKEN_PIPESL_1_A 0x420b0
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#define _CHICKEN_PIPESL_1_B 0x420b4
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@ -58,6 +58,10 @@ static void bxt_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* See Bspec note for PSR2_CTL bit 31, Wa#828:bxt */
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I915_WRITE(CHICKEN_PAR1_1,
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I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
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/* WaDisableSDEUnitClockGating:bxt */
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I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
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GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
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@ -6698,6 +6702,15 @@ static void lpt_suspend_hw(struct drm_device *dev)
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}
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}
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static void skylake_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,kbl */
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I915_WRITE(CHICKEN_PAR1_1,
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I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
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}
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static void broadwell_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -7163,9 +7176,9 @@ static void nop_init_clock_gating(struct drm_device *dev)
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void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
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{
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if (IS_SKYLAKE(dev_priv))
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dev_priv->display.init_clock_gating = nop_init_clock_gating;
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dev_priv->display.init_clock_gating = skylake_init_clock_gating;
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else if (IS_KABYLAKE(dev_priv))
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dev_priv->display.init_clock_gating = nop_init_clock_gating;
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dev_priv->display.init_clock_gating = skylake_init_clock_gating;
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else if (IS_BROXTON(dev_priv))
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dev_priv->display.init_clock_gating = bxt_init_clock_gating;
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else if (IS_BROADWELL(dev_priv))
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