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perf/x86/intel/lbr: Add a function pointer for LBR read

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The method to read Architectural LBRs is different from previous
model-specific LBR. Perf has to implement a different function.

A function pointer for LBR read is introduced. Perf should initialize
the corresponding function at boot time, and avoid checking lbr_format
at run time.

The current 64-bit LBR read function is set as default.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1593780569-62993-4-git-send-email-kan.liang@linux.intel.com
This commit is contained in:
Kan Liang 2020-07-03 05:49:09 -07:00 committed by Peter Zijlstra
parent 9f354a726c
commit c301b1d80e
3 changed files with 13 additions and 7 deletions
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6
arch/x86/events/intel/core.c
View File

@ -3980,6 +3980,7 @@ static __initconst const struct x86_pmu core_pmu = {
.check_period = intel_pmu_check_period,
.lbr_reset = intel_pmu_lbr_reset_64,
.lbr_read = intel_pmu_lbr_read_64,
};
static __initconst const struct x86_pmu intel_pmu = {
@ -4027,6 +4028,7 @@ static __initconst const struct x86_pmu intel_pmu = {
.aux_output_match = intel_pmu_aux_output_match,
.lbr_reset = intel_pmu_lbr_reset_64,
.lbr_read = intel_pmu_lbr_read_64,
};
static __init void intel_clovertown_quirk(void)
@ -4653,8 +4655,10 @@ __init int intel_pmu_init(void)
x86_pmu.intel_cap.capabilities = capabilities;
}
if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
x86_pmu.lbr_read = intel_pmu_lbr_read_32;
}
intel_ds_init();

9
arch/x86/events/intel/lbr.c
View File

@ -562,7 +562,7 @@ void intel_pmu_lbr_disable_all(void)
__intel_pmu_lbr_disable();
}
static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
{
unsigned long mask = x86_pmu.lbr_nr - 1;
u64 tos = intel_pmu_lbr_tos();
@ -599,7 +599,7 @@ static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
* is the same as the linear address, allowing us to merge the LIP and EIP
* LBR formats.
*/
static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
{
bool need_info = false, call_stack = false;
unsigned long mask = x86_pmu.lbr_nr - 1;
@ -704,10 +704,7 @@ void intel_pmu_lbr_read(void)
cpuc->lbr_users == cpuc->lbr_pebs_users)
return;
if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
intel_pmu_lbr_read_32(cpuc);
else
intel_pmu_lbr_read_64(cpuc);
x86_pmu.lbr_read(cpuc);
intel_pmu_lbr_filter(cpuc);
}

5
arch/x86/events/perf_event.h
View File

@ -694,6 +694,7 @@ struct x86_pmu {
bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
void (*lbr_reset)(void);
void (*lbr_read)(struct cpu_hw_events *cpuc);
/*
* Intel PT/LBR/BTS are exclusive
@ -1085,6 +1086,10 @@ void intel_pmu_lbr_disable_all(void);
void intel_pmu_lbr_read(void);
void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc);
void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc);
void intel_pmu_lbr_init_core(void);
void intel_pmu_lbr_init_nhm(void);